Alternatives and similar repositories for rvv-intrinsic-doc

Users that are interested in rvv-intrinsic-doc are comparing it to the libraries listed below

• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆122Updated 9 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆152Updated 7 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆127Updated last week
• howjmay / neon2rvv
  A translator from ARM NEON intrinsics to RISCV-V Extension implementation
  ☆38Updated 3 weeks ago
• rivosinc / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆11Updated 3 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆187Updated this week
• sparcians / map
  Modeling Architectural Platform
  ☆203Updated 3 weeks ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆462Updated last month
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated last year
• riscvarchive / riscv-v-spec
  Working draft of the proposed RISC-V V vector extension
  ☆1,046Updated last year
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆322Updated 9 months ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated last week
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆425Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆90Updated this week
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆304Updated 4 months ago
• umd-memsys / DRAMsim3
  DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
  ☆409Updated last year
• vortexgpgpu / vortex_tutorials
  ☆181Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆294Updated last year
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆275Updated last year
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆478Updated last year
• CMU-SAFARI / ramulator2
  Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …
  ☆392Updated last month
• OpenXiangShan / GEM5
  ☆101Updated this week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated 2 weeks ago
• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆163Updated 2 weeks ago
• CMU-SAFARI / ramulator
  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …
  ☆656Updated 2 years ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆103Updated 6 years ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆246Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆804Updated this week
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆59Updated last year
• umd-memsys / DRAMSim2
  DRAMSim2: A cycle accurate DRAM simulator
  ☆279Updated 4 years ago