riscv-non-isa / rvv-intrinsic-doc
☆330Updated last week
Alternatives and similar repositories for rvv-intrinsic-doc
Users that are interested in rvv-intrinsic-doc are comparing it to the libraries listed below
Sorting:
- RiVEC Bencmark Suite☆114Updated 5 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆112Updated last week
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆149Updated this week
- RISC-V Packed SIMD Extension☆144Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆142Updated 3 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆165Updated 3 weeks ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆424Updated last week
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆31Updated 8 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆151Updated 3 years ago
- RISC-V Architecture Profiles☆148Updated 3 months ago
- RISC-V Proxy Kernel☆632Updated 2 weeks ago
- A scalable High-Level Synthesis framework on MLIR☆258Updated last year
- Modeling Architectural Platform☆187Updated this week
- Working draft of the proposed RISC-V V vector extension☆1,028Updated last year
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆735Updated last week
- Unit tests generator for RVV 1.0☆84Updated last month
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆328Updated last week
- Instruction Set Generator initially contributed by Futurewei☆279Updated last year
- ☆150Updated last year
- Working draft of the proposed RISC-V Bitmanipulation extension☆210Updated last year
- ☆171Updated 2 weeks ago
- Documentation for RISC-V Spike☆100Updated 6 years ago
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆160Updated 5 months ago
- RISC-V Torture Test☆194Updated 10 months ago
- ☆560Updated this week
- Wrapper for Rocket-Chip on FPGAs☆133Updated 2 years ago
- RISC-V cryptography extensions standardisation work.☆387Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 5 months ago
- Berkeley's Spatial Array Generator☆946Updated last month