riscv-non-isa / rvv-intrinsic-doc
☆282Updated this week
Related projects: ⓘ
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆142Updated last week
- RISC-V Packed SIMD Extension☆138Updated 10 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆350Updated this week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆130Updated 3 weeks ago
- Modeling Architectural Platform☆156Updated this week
- ☆150Updated 6 months ago
- RiVEC Bencmark Suite☆88Updated 3 weeks ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆535Updated last week
- Working draft of the proposed RISC-V Bitmanipulation extension☆203Updated 5 months ago
- Instruction Set Generator initially contributed by Futurewei☆255Updated 11 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆143Updated 2 years ago
- RISC-V SystemC-TLM simulator☆269Updated last month
- A matrix extension proposal for AI applications under RISC-V architecture☆93Updated 2 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆12Updated 2 years ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆383Updated 5 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆210Updated last week
- A scalable High-Level Synthesis framework on MLIR☆217Updated 4 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆77Updated 2 weeks ago
- RISC-V Proxy Kernel☆581Updated last week
- Sail RISC-V model☆428Updated this week
- RISC-V Torture Test☆163Updated 2 months ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆217Updated 2 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆237Updated this week
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆296Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆225Updated this week
- ☆501Updated 2 weeks ago
- ☆111Updated this week
- PLIC Specification☆130Updated last year
- ☆154Updated 9 months ago
- RISC-V cryptography extensions standardisation work.☆359Updated 6 months ago