Alternatives and similar repositories for rocket_chip_vpu

Users that are interested in rocket_chip_vpu are comparing it to the libraries listed below

• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 7 months ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated this week
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Updated 5 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆12Updated 2 months ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated this week
• embecosm / embecosm-toolchain-releases
  ☆16Updated last month
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆35Updated last year
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆47Updated 7 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 5 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 2 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• 0ctobyte / procyon
  Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.
  ☆12Updated 2 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆55Updated 3 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• rdolbeau / VexRiscvBPluginGenerator
  ☆17Updated 2 years ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆57Updated 2 years ago