UCTECHIP / rocket_chip_vpuLinks
☆11Updated 5 years ago
Alternatives and similar repositories for rocket_chip_vpu
Users that are interested in rocket_chip_vpu are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- RV64GC Linux Capable RISC-V Core☆51Updated 2 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- ☆89Updated 4 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆108Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆134Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- 64-bit multicore Linux-capable RISC-V processor☆104Updated 8 months ago
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆76Updated last month
- RISC-V Nexus Trace TG documentation and reference code☆56Updated last year
- Unit tests generator for RVV 1.0☆99Updated 2 months ago
- PCI Express controller model☆71Updated 3 years ago
- ☆192Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆80Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆126Updated 3 months ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Clarvi simple RISC-V processor for teaching☆58Updated 8 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 4 years ago
- RISC-V Virtual Prototype☆46Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆76Updated last month
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆114Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year