compiler-dev / llvm-rvLinks
Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
☆43Updated 4 years ago
Alternatives and similar repositories for llvm-rv
Users that are interested in llvm-rv are comparing it to the libraries listed below
Sorting:
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 9 months ago
- RiVEC Bencmark Suite☆124Updated last year
- ☆107Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆126Updated 9 months ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆49Updated this week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆30Updated 2 weeks ago
- ☆46Updated 6 years ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆44Updated 2 years ago
- Example code for Modern SystemC using Modern C++☆68Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆55Updated 8 years ago
- ☆57Updated 6 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆113Updated 2 years ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆78Updated 5 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆80Updated this week
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Public release☆58Updated 6 years ago
- ☆81Updated last year
- A scalable High-Level Synthesis framework on MLIR☆284Updated last year
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- ☆40Updated 8 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆76Updated 2 months ago
- ☆16Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- ☆66Updated 3 years ago