Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
☆44Dec 21, 2020Updated 5 years ago
Alternatives and similar repositories for llvm-rv
Users that are interested in llvm-rv are comparing it to the libraries listed below
Sorting:
- ☆10Sep 1, 2020Updated 5 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- ☆11Jan 9, 2021Updated 5 years ago
- ☆13Nov 25, 2019Updated 6 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- ☆365Updated this week
- ☆15Oct 2, 2023Updated 2 years ago
- Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V☆19Apr 26, 2020Updated 5 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。☆30Sep 18, 2025Updated 6 months ago
- RuyiSDK Package Manager☆34Feb 12, 2026Updated last month
- The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github…☆31Updated this week
- Security Test Benchmark for Computer Architectures☆20Sep 24, 2025Updated 5 months ago
- KernelFaRer: Replacing Native-Code Idioms with High-Performance Library Calls☆12Sep 7, 2025Updated 6 months ago
- Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.☆23Jan 24, 2026Updated last month
- Example of RISC-V Vector programming☆27Sep 4, 2025Updated 6 months ago
- Andes DSP Library☆20Dec 15, 2025Updated 3 months ago
- Vector processor for RISC-V vector ISA☆140Oct 19, 2020Updated 5 years ago
- a Halide language To MLIR compiler.☆26Aug 30, 2021Updated 4 years ago
- Chunky Loop Interaction☆25Aug 13, 2019Updated 6 years ago
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- MLIRX is now defunct. Please see PolyBlocks - https://docs.polymagelabs.com☆38Dec 1, 2023Updated 2 years ago
- "Very low cost, tiny (USB thumb size) FPGA board. 1st board with Efinix Trion FPGA and comes with Efinity IDE Solder or unsoldered versio…☆25Nov 11, 2019Updated 6 years ago
- Translate RISC-V Vector Assembly from v1.0 to v0.7☆36Aug 21, 2024Updated last year
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 5 months ago
- Basic start of TensorFlow with TensorBoard☆11Apr 9, 2016Updated 9 years ago
- Conversions to MLIR EmitC☆135Dec 12, 2024Updated last year
- ☆10Mar 14, 2018Updated 8 years ago
- RSSI-based OFDM signal classification using a machine learning algorithm.☆12May 15, 2018Updated 7 years ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆29Oct 20, 2024Updated last year
- ☆10Aug 10, 2018Updated 7 years ago
- ☆193Aug 30, 2021Updated 4 years ago
- LLM Agent for Hardware Description Language☆21Jun 7, 2025Updated 9 months ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Mar 8, 2026Updated last week
- ☆16Oct 26, 2017Updated 8 years ago
- npx vincent0700-cli☆15Jun 1, 2021Updated 4 years ago
- ☆11Dec 31, 2019Updated 6 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆165Feb 11, 2025Updated last year
- A blog for LLVM(v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM.☆14Jun 17, 2022Updated 3 years ago