compiler-dev / llvm-rv
Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
☆43Updated 4 years ago
Alternatives and similar repositories for llvm-rv:
Users that are interested in llvm-rv are comparing it to the libraries listed below
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- ☆90Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆22Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆124Updated last week
- upstream: https://github.com/RALC88/gem5☆31Updated last year
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 4 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆41Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆59Updated 2 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆14Updated 10 months ago
- ☆42Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year
- ☆41Updated 6 years ago
- RiVEC Bencmark Suite☆109Updated 2 months ago
- Unit tests generator for RVV 1.0☆74Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆69Updated 5 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- Championship Value Prediction (CVP) simulator.☆15Updated 4 years ago
- Release of stream-specialization software/hardware stack.☆120Updated last year
- SystemC training aimed at TLM.☆27Updated 4 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆27Updated 10 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 7 months ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Updated 2 years ago
- Spike with a coherence supported cache model☆13Updated 7 months ago
- ☆28Updated 4 months ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆23Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆61Updated last year
- Public release☆49Updated 5 years ago