Alternatives and similar repositories for rvv-examples

Users that are interested in rvv-examples are comparing it to the libraries listed below

• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆118Updated 8 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆150Updated 5 months ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆266Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆36Updated last month
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆45Updated last week
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆41Updated 2 years ago
• accel-sim / gpgpu-sim_distribution
  GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated…
  ☆54Updated 3 weeks ago
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆32Updated last year
• suchandler96 / gem5-NVDLA
  ☆33Updated 4 months ago
• zeasa / nvdla-compiler
  ☆46Updated 5 years ago
• areuther / ai-accelerators
  CSV spreadsheets and other material for AI accelerator survey papers
  ☆173Updated last year
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 8 months ago
• THU-DSP-LAB / llvm-project
  LLVM OpenCL C compiler suite for ventus GPGPU
  ☆51Updated this week
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆107Updated 2 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆32Updated 2 years ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆135Updated 5 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• OpenXiangShan / GEM5
  ☆93Updated this week
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆30Updated 5 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆31Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆104Updated 5 months ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆190Updated 4 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆68Updated last year
• Xilinx / mlir-air
  ☆102Updated last week
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆28Updated last week
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆60Updated 7 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆110Updated last year