Alternatives and similar repositories for rvv-examples

Users that are interested in rvv-examples are comparing it to the libraries listed below

• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆120Updated 8 months ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆108Updated 2 years ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆151Updated 6 months ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆45Updated last month
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆108Updated 3 months ago
• Xilinx / mlir-air
  ☆104Updated this week
• suchandler96 / gem5-NVDLA
  ☆33Updated 4 months ago
• riscv-stc / riscv-matrix-spec
  RISC-V Matrix Specification
  ☆22Updated 8 months ago
• THU-DSP-LAB / llvm-project
  LLVM OpenCL C compiler suite for ventus GPGPU
  ☆52Updated 3 weeks ago
• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• accel-sim / gpgpu-sim_distribution
  GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated…
  ☆54Updated this week
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆41Updated 2 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆22Updated 4 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆36Updated 2 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆120Updated last month
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• pulp-platform / redmule
  ☆72Updated last week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• riscv / integrated-matrix-extension
  RISC-V Integrated Matrix Development Repository
  ☆16Updated 10 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆74Updated last week
• LeiWang1999 / nvdla_loadables
  some sample caffemodel, prototxt, test images and pre compiled loadabes .
  ☆13Updated 4 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• riscv / riscv-bfloat16
  ☆37Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 3 months ago
• pku-liang / ksim
  ☆45Updated 7 months ago
• tenstorrent / whisper
  ☆53Updated 2 weeks ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated 2 weeks ago