plctlab / llvm-project
PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
☆159Updated last week
Related projects ⓘ
Alternatives and complementary repositories for llvm-project
- 平头哥玄 铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆62Updated 3 years ago
- ☆236Updated this week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆41Updated 4 years ago
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆193Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆116Updated this week
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆74Updated 4 years ago
- RiVEC Bencmark Suite☆104Updated this week
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated last year
- SiFive's LLVM working tree☆83Updated 3 months ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆41Updated 3 years ago
- ☆118Updated this week
- XiangShan Frontend Develop Environment☆45Updated last week
- ☆66Updated this week
- ☆164Updated 3 years ago
- ☆115Updated 2 years ago
- ☆55Updated last year
- Run rocket-chip on FPGA☆60Updated 4 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆159Updated 3 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆46Updated 3 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆105Updated last week
- Training Materials for RISC-V HW/SW, focusing on compilers, emulators, and virtual machines. provided by PLCT Lab.☆33Updated 6 months ago
- PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。☆26Updated 3 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆114Updated 3 weeks ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆52Updated 10 months ago
- ☆45Updated last week
- A translation project of the RISC-V reader☆175Updated 10 months ago
- Wrapper for Rocket-Chip on FPGAs☆124Updated 2 years ago
- Modeling Architectural Platform☆167Updated this week
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆194Updated 4 years ago