Alternatives and similar repositories for rvv_example

Users that are interested in rvv_example are comparing it to the libraries listed below

• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆113Updated last week
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆131Updated last week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆152Updated last year
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated last week
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆180Updated this week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆97Updated 5 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆60Updated last week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 4 months ago
• riscv-admin / graphics
  Graphics SIG organizational information
  ☆39Updated last year
• bsc-loca / sargantana
  ☆108Updated last month
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆136Updated last week
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last month
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆38Updated last month
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated last week
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated 2 weeks ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated last week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆74Updated last year
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated 2 years ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated last week
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆66Updated 8 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated 2 weeks ago