brucehoult / rvv_exampleLinks
Simple demonstration of using the RISC-V Vector extension
☆47Updated last year
Alternatives and similar repositories for rvv_example
Users that are interested in rvv_example are comparing it to the libraries listed below
Sorting:
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆125Updated last month
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆156Updated 3 years ago
- Chisel RISC-V Vector 1.0 Implementation☆108Updated 3 months ago
- 64-bit multicore Linux-capable RISC-V processor☆96Updated 4 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated last week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- ☆90Updated this week
- ☆62Updated 4 years ago
- RISC-V Packed SIMD Extension☆150Updated last year
- Vector Acceleration IP core for RISC-V*☆183Updated 3 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆174Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 3 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆74Updated 2 weeks ago
- ☆147Updated last year
- The multi-core cluster of a PULP system.☆108Updated last week
- Unit tests generator for RVV 1.0☆89Updated 3 weeks ago
- ☆107Updated 2 weeks ago
- The specification for the FIRRTL language☆63Updated 2 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆175Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 10 months ago
- ☆53Updated 3 weeks ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆34Updated 3 weeks ago
- Documentation of the RISC-V C API☆77Updated last month
- Translate RISC-V Vector Assembly from v1.0 to v0.7☆34Updated last year
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆45Updated 3 years ago
- RISC-V IOMMU Specification☆128Updated last week