Alternatives and similar repositories for c910-llvm:

Users that are interested in c910-llvm are comparing it to the libraries listed below

• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆160Updated 2 months ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• plctlab / rvv-benchmark
  PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases
  ☆21Updated 4 years ago
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆109Updated 2 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆57Updated last year
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆31Updated 6 years ago
• riscv / riscv-bfloat16
  ☆33Updated 7 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆124Updated this week
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆51Updated this week
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆58Updated last year
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 4 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆40Updated this week
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 10 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆48Updated 3 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• sifive / riscv-llvm
  SiFive's LLVM working tree
  ☆85Updated 6 months ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆75Updated 4 years ago
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆43Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆132Updated this week
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆73Updated last week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆149Updated last year
• riscv / riscv-CMOs
  ☆83Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆89Updated last year
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 6 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆58Updated 2 years ago
• OpenXiangShan / GEM5
  ☆74Updated this week