ISRC-CAS / c910-llvmLinks
平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本
☆70Updated 4 years ago
Alternatives and similar repositories for c910-llvm
Users that are interested in c910-llvm are comparing it to the libraries listed below
Sorting:
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆160Updated 6 months ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated 2 years ago
- upstream: https://github.com/RALC88/gem5☆31Updated 2 years ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- RiVEC Bencmark Suite☆117Updated 6 months ago
- XiangShan Frontend Develop Environment☆59Updated this week
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆77Updated 5 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆148Updated 4 months ago
- ☆91Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆102Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆86Updated 3 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆48Updated this week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- ☆122Updated 2 years ago
- ☆42Updated 3 years ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆34Updated 9 months ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆39Updated 7 months ago
- Open-source high-performance non-blocking cache☆83Updated 3 weeks ago
- Ventus GPGPU ISA Simulator Based on Spike☆43Updated last week
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Unit tests generator for RVV 1.0☆88Updated last month
- Modern co-simulation framework for RISC-V CPUs☆146Updated this week
- ☆61Updated 2 years ago