Alternatives and similar repositories for DREAMPlaceFPGA

Users that are interested in DREAMPlaceFPGA are comparing it to the libraries listed below

• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated 2 weeks ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• IntelLabs / FloorSet
  ☆74Updated 2 months ago
• NVlabs / INSTA
  ☆85Updated 2 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆51Updated 2 months ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆39Updated 2 years ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆28Updated last year
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• vaughnbetz / COFFE
  ☆44Updated 11 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆60Updated last year
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated 2 weeks ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 9 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆151Updated 4 months ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆49Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• parallaxsw / OpenSTA
  ☆82Updated this week
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆55Updated 7 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆19Updated 3 months ago
• The-OpenROAD-Project / asap5
  ☆34Updated 2 years ago
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆113Updated last year
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆122Updated 2 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆53Updated 2 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 5 months ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆175Updated 3 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆45Updated 2 months ago