Blaok / tapaLinks
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators. [See https://github.com/UCLA-VAST/tapa for issues & pull requests]
☆19Updated last year
Alternatives and similar repositories for tapa
Users that are interested in tapa are comparing it to the libraries listed below
Sorting:
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 3 months ago
- DASS HLS Compiler☆29Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆30Updated 6 years ago
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆18Updated 3 years ago
- ☆36Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆60Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- ☆29Updated 8 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- ☆25Updated last year
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 4 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆37Updated last week
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆21Updated 7 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆17Updated 3 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 6 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- ☆14Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago