Blaok / tapa
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators. [See https://github.com/UCLA-VAST/tapa for issues & pull requests]
☆19Updated 7 months ago
Alternatives and similar repositories for tapa:
Users that are interested in tapa are comparing it to the libraries listed below
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated last week
- DASS HLS Compiler☆29Updated last year
- ☆12Updated 8 months ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated 3 weeks ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆18Updated last year
- ☆29Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 8 years ago
- ☆15Updated 2 years ago
- ☆26Updated 7 years ago
- Xilinx Modifications to Halide☆12Updated 3 years ago
- ☆35Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆23Updated 2 years ago
- Falcon Merlin Compiler☆39Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 2 weeks ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago