Blaok / tapa
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators. [See https://github.com/UCLA-VAST/tapa for issues & pull requests]
☆19Updated 5 months ago
Alternatives and similar repositories for tapa:
Users that are interested in tapa are comparing it to the libraries listed below
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆20Updated last week
- DASS HLS Compiler☆27Updated last year
- A polyhedral compiler for hardware accelerators☆55Updated 6 months ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- ☆27Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- ☆12Updated 5 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆22Updated 4 months ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 3 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- ☆23Updated 4 years ago
- ☆15Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆17Updated 8 years ago
- ☆23Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆17Updated 6 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆21Updated 2 weeks ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Falcon Merlin Compiler☆38Updated 4 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆18Updated last year