Blaok / tapa
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators. [See https://github.com/UCLA-VAST/tapa for issues & pull requests]
☆19Updated 8 months ago
Alternatives and similar repositories for tapa:
Users that are interested in tapa are comparing it to the libraries listed below
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated 2 weeks ago
- ☆12Updated 9 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- ☆29Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆39Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 9 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Xilinx Modifications to Halide☆12Updated 4 years ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated 11 months ago
- ☆35Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated 2 years ago
- ☆27Updated 7 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆25Updated 2 years ago
- ☆24Updated 4 years ago
- Falcon Merlin Compiler☆39Updated 4 years ago
- ☆15Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- ☆15Updated 4 years ago