Blaok / tapaLinks
TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerators. [See https://github.com/UCLA-VAST/tapa for issues & pull requests]
☆19Updated last year
Alternatives and similar repositories for tapa
Users that are interested in tapa are comparing it to the libraries listed below
Sorting:
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 2 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 6 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆20Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆29Updated 8 years ago
- ☆25Updated last year
- An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE☆17Updated 3 years ago
- ☆13Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- ☆60Updated 2 years ago
- ☆24Updated 5 years ago
- ☆30Updated 6 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- ☆36Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆22Updated 10 months ago
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- ☆17Updated 2 years ago