Alternatives and similar repositories for tapa

Users that are interested in tapa are comparing it to the libraries listed below

• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆22Updated 3 weeks ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 8 years ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• wincle626 / HLS_Legup
  ☆28Updated 7 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆29Updated 2 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆59Updated last year
• icgrp / hipr
  ☆16Updated 2 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• Xilinx / merlin-compiler
  ☆58Updated 2 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• Xilinx / hydra
  ☆13Updated 3 years ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 2 months ago
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆18Updated 6 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• he-actlab / polymath
  ☆22Updated 6 months ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• hanchenye / polyaie
  An MLIR-based compiler from C/C++ to AMD-Xilinx Versal AIE
  ☆16Updated 3 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• fpgasystems / GPU-FPGA-Recommendation-System
  FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
  ☆16Updated 4 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 7 months ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• UCLA-VAST / splag
  Accelerating SSSP for power-law graphs using an FPGA.
  ☆23Updated 3 years ago
• CMU-SAFARI / SPARTA
  A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…
  ☆22Updated 2 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆39Updated last week
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆60Updated 3 years ago