ABKGroup / TritonPart
The first version of TritonPart
☆18Updated 8 months ago
Related projects: ⓘ
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆72Updated this week
- ☆46Updated last month
- GPU-based logic synthesis tool☆65Updated 2 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆96Updated 6 months ago
- ☆18Updated 4 months ago
- Collection of digital hardware modules & projects (benchmarks)☆27Updated 3 weeks ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆45Updated 2 months ago
- ☆17Updated last year
- ☆18Updated 2 months ago
- ☆33Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆28Updated 3 months ago
- Dataset for ML-guided Accelerator Design☆30Updated 5 months ago
- ☆29Updated 11 months ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆54Updated 5 months ago
- ☆24Updated 9 months ago
- A list of our chiplet simulaters☆18Updated 3 years ago
- ☆24Updated 3 years ago
- DATC Robust Design Flow.☆37Updated 4 years ago
- The open-sourced version of BOOM-Explorer☆31Updated last year
- ☆34Updated 5 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆15Updated 2 months ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 6 years ago
- Artificial Netlist Generator☆29Updated 6 months ago
- ☆15Updated 2 years ago
- DATC RDF☆48Updated 4 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆50Updated 4 years ago
- Material for OpenROAD Tutorial at DAC 2020☆45Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆22Updated 4 years ago
- Bounded-Skew DME v1.3☆13Updated 6 years ago
- ☆20Updated 3 years ago