Alternatives and similar repositories for TritonPart

Users that are interested in TritonPart are comparing it to the libraries listed below

• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆25Updated 2 weeks ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 10 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 3 weeks ago
• zshi0616 / python-deepgate
  ☆22Updated 11 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆48Updated last week
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated last month
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆104Updated last year
• tsung-wei-huang / ece5960-physical-design
  ☆38Updated 2 years ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆44Updated 3 weeks ago
• cuhk-eda / cu-gr-2
  ☆44Updated last year
• bu-icsg / TAP-2.5D
  ☆33Updated 4 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated last month
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆48Updated 4 months ago
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆122Updated last week
• zshi0616 / DeepGate2
  ☆28Updated last year
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• NVlabs / Differentiable-Global-Router
  ☆18Updated 6 months ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆39Updated 7 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆20Updated 2 years ago
• cuhk-eda / GCS-Timer
  ☆20Updated 7 months ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆68Updated this week
• RIOSLaboratory / Open3DFlow
  An open-source 3D IC design platform that leverages existing open EDA tools while incorporating tailored abstractions and customizations …
  ☆28Updated this week
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆28Updated 3 years ago
• ABKGroup / BlobPlacement
  ☆13Updated 11 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago