🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
☆183Apr 25, 2025Updated last year
Alternatives and similar repositories for OpenPARF
Users that are interested in OpenPARF are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆116Mar 9, 2024Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆97Apr 30, 2025Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆169Jul 8, 2026Updated last month
- Deep learning toolkit-enabled VLSI placement☆1,035Jul 18, 2026Updated 3 weeks ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆93Feb 11, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆32Oct 12, 2023Updated 2 years ago
- Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source☆343Jan 5, 2026Updated 7 months ago
- The first version of TritonPart☆38Jul 25, 2026Updated 2 weeks ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆199May 19, 2025Updated last year
- ☆54Jan 3, 2024Updated 2 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆153Feb 27, 2023Updated 3 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,257Updated this week
- Build Customized FPGA Implementations for Vivado☆383Updated this week
- GPU-based logic synthesis tool☆110Mar 31, 2026Updated 4 months ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆25May 8, 2025Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆37Jun 3, 2025Updated last year
- ☆110Jun 20, 2025Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆40Jan 16, 2025Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆140Jul 20, 2024Updated 2 years ago
- [NeurIPS 2022 Spotlight] MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning☆72Jan 5, 2026Updated 7 months ago
- ☆40Nov 3, 2020Updated 5 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆710Dec 26, 2025Updated 7 months ago
- ☆17Mar 26, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆168Jul 12, 2023Updated 3 years ago
- SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)☆31Apr 8, 2023Updated 3 years ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆90Aug 4, 2026Updated last week
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)☆503May 17, 2026Updated 2 months ago
- ☆19Jul 2, 2024Updated 2 years ago
- An open-source EDA infrastructure and tools from netlist to GDS☆539Jul 9, 2026Updated last month
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆213May 21, 2026Updated 2 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆130Dec 20, 2022Updated 3 years ago
- Taiwei-3D-Flow☆60Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A hardware synthesis framework with multi-level paradigm☆45Jan 10, 2025Updated last year
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆2,972Updated this week
- C++ logic network library☆303Aug 7, 2026Updated last week
- VLSI EDA Global Router☆85Feb 15, 2026Updated 5 months ago
- RePlAce global placement tool☆255Aug 13, 2020Updated 6 years ago
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆34Jun 17, 2026Updated last month