TILOS-AI-Institute / HypergraphPartitioningLinks
Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
☆70Updated 2 months ago
Alternatives and similar repositories for HypergraphPartitioning
Users that are interested in HypergraphPartitioning are comparing it to the libraries listed below
Sorting:
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆77Updated last year
- GPU-based logic synthesis tool☆90Updated 3 weeks ago
- The first version of TritonPart☆28Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆135Updated 2 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 3 months ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆28Updated last year
- ☆24Updated 2 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆130Updated last month
- Artificial Netlist Generator☆40Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 7 months ago
- ☆31Updated 4 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆50Updated 2 months ago
- Rsyn – An Extensible Physical Synthesis Framework☆129Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- ☆24Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆32Updated last month
- ☆74Updated 2 months ago
- ☆39Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 3 months ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆60Updated last month
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- EPFL logic synthesis benchmarks☆208Updated last month
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆47Updated 2 months ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated last year
- ☆23Updated 9 months ago
- ☆22Updated last year
- ☆85Updated 2 months ago
- ☆31Updated 3 years ago