arc-research-lab / AIM

Related projects ⓘ

Alternatives and complementary repositories for AIM

• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆80Updated last month
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆38Updated 6 months ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆49Updated last year
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆24Updated last year
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆19Updated this week
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆71Updated 3 months ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆19Updated this week
• sfu-arch / SpGEMM
  ☆33Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆44Updated 2 years ago
• cucapra / EventQueue
  EQueue Dialect
  ☆39Updated 2 years ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆68Updated last year
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆26Updated 4 months ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆52Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆53Updated last month
• awai54st / Logic-Shrinkage
  ☆20Updated 2 years ago
• icgrp / hipr
  ☆14Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆38Updated 8 months ago
• UCLA-VAST / FlexCNN
  ☆70Updated last year
• SFU-HiAccel / CHIP-KNN
  [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs
  ☆14Updated 7 months ago
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆29Updated 2 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆21Updated 3 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆59Updated 3 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆46Updated 2 weeks ago
• UIUC-ChenLab / Nimblock
  ☆10Updated last year
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆32Updated last year
• VeriGOOD-ML / public
  ☆51Updated 10 months ago