Alternatives and similar repositories for AIM

Users that are interested in AIM are comparing it to the libraries listed below

• Xilinx / SLASH
  A research shell for Alveo V80
  ☆17Updated this week
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆58Updated 5 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆83Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆68Updated 5 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• CastLab-KAIST / OpenMDS
  ☆14Updated 2 years ago
• hplp / PiMulator
  Processing in Memory Emulation
  ☆21Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated 2 months ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆83Updated 2 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆38Updated 9 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 3 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆40Updated this week
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆61Updated 11 months ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆28Updated last year
• pnnl / soda-opt
  ☆49Updated 2 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆47Updated 6 months ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆59Updated 3 years ago
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆15Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 5 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆62Updated 3 weeks ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆38Updated last month
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆39Updated 4 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week