Xilinx / fpga24_routing_contest
Runtime-First FPGA Interchange Routing Contest @ FPGA’24
☆32Updated last month
Alternatives and similar repositories for fpga24_routing_contest:
Users that are interested in fpga24_routing_contest are comparing it to the libraries listed below
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 4 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- Open source process design kit for 28nm open process☆52Updated 11 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆30Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- ☆31Updated 3 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 5 years ago
- ☆34Updated 5 years ago
- ☆43Updated 5 years ago
- A configurable SRAM generator☆47Updated 3 months ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- sram/rram/mram.. compiler☆33Updated last year
- ☆55Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆79Updated 3 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆32Updated 2 months ago
- ☆25Updated 11 months ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- DASS HLS Compiler☆29Updated last year
- For contributions of Chisel IP to the chisel community.☆60Updated 5 months ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆122Updated 2 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago