Xilinx / fpga24_routing_contestLinks
Runtime-First FPGA Interchange Routing Contest @ FPGA’24
☆33Updated 2 months ago
Alternatives and similar repositories for fpga24_routing_contest
Users that are interested in fpga24_routing_contest are comparing it to the libraries listed below
Sorting:
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- DASS HLS Compiler☆29Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 8 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆87Updated last year
- Next generation CGRA generator☆112Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- Open source process design kit for 28nm open process☆60Updated last year
- sram/rram/mram.. compiler☆37Updated last year
- ☆44Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 6 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated 2 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- ☆32Updated 6 months ago
- Library of open source Process Design Kits (PDKs)☆49Updated last month
- ☆86Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- Open Source PHY v2☆29Updated last year
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago