Xilinx / fpga24_routing_contestLinks
Runtime-First FPGA Interchange Routing Contest @ FPGA’24
☆33Updated 2 months ago
Alternatives and similar repositories for fpga24_routing_contest
Users that are interested in fpga24_routing_contest are comparing it to the libraries listed below
Sorting:
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 9 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A configurable SRAM generator☆53Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- sram/rram/mram.. compiler☆38Updated last year
- Next generation CGRA generator☆113Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- EDA physical synthesis optimization kit☆60Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- ☆32Updated 7 months ago
- ☆44Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- ☆19Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated 3 months ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- ☆49Updated 4 months ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Project repo for the POSH on-chip network generator☆49Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆50Updated last week
- Open source process design kit for 28nm open process☆60Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago