Blaok / sodaLinks
Stencil with Optimized Dataflow Architecture
☆12Updated last year
Alternatives and similar repositories for soda
Users that are interested in soda are comparing it to the libraries listed below
Sorting:
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆27Updated 5 years ago
- ☆72Updated 2 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- ☆16Updated 3 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆20Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- ☆16Updated 7 years ago
- Fast Floating Point Operators for High Level Synthesis☆22Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 6 months ago
- ☆16Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- An HBM FPGA based SpMV Accelerator☆14Updated last year
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- ☆36Updated 4 years ago
- ☆15Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆24Updated last year
- A collection of URLs related to High Level Synthesis (HLS).☆13Updated 4 years ago