Alternatives and similar repositories for soda:

Users that are interested in soda are comparing it to the libraries listed below

• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆3Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 3 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆23Updated last month
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆18Updated 9 months ago
• lukasc-ch / ExtendedBitPlaneCompression
  Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…
  ☆17Updated 5 years ago
• UIUC-ChenLab / rip
  ☆16Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆19Updated 2 years ago
• ic-lab-duth / Fast-Float4HLS
  Fast Floating Point Operators for High Level Synthesis
  ☆20Updated last year
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆12Updated 3 years ago
• sharc-lab / DGNN-Booster
  ☆16Updated last year
• aravinds92 / Systolic-Array
  Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
  ☆12Updated 8 years ago
• priyanka-raina / dnn-accelerator
  ☆13Updated 4 years ago
• Kareem-Emad / DCNN-Accelerator
  Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.
  ☆12Updated 5 years ago
• synergy-noc-generators / Proteus
  ☆9Updated last year
• template-hls / template-hls-float
  ☆27Updated 5 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• nimish15shah / DAG_Processor
  A DAG processor and compiler for a tree-based spatial datapath.
  ☆13Updated 2 years ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆25Updated 9 months ago
• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆10Updated 4 years ago
• pku-dasys / easymac
  ☆16Updated 2 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆33Updated 4 years ago
• ic-lab-duth / DRIM4HLS
  DUTH RISC V Microprocessor for High Level Synthesis
  ☆10Updated last year
• lite-david / comet
  RISC-V ISA based 32-bit processor written in HLS
  ☆17Updated 5 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• cornell-zhang / uptune
  A Generic Distributed Auto-Tuning Infrastructure
  ☆21Updated 3 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year