watcag / RapidLayoutLinks
RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms
☆18Updated 4 years ago
Alternatives and similar repositories for RapidLayout
Users that are interested in RapidLayout are comparing it to the libraries listed below
Sorting:
- ☆60Updated 2 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- ☆71Updated 2 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆23Updated 3 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- ☆27Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- Project repo for the POSH on-chip network generator☆48Updated 3 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated last month
- ☆36Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 2 months ago
- A configurable SRAM generator☆53Updated last week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆50Updated 3 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated last month
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆11Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- DASS HLS Compiler☆29Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆43Updated 10 months ago
- ☆15Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago