A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
☆33Aug 21, 2024Updated last year
Alternatives and similar repositories for ReGDS-Logic-Gate-Extraction
Users that are interested in ReGDS-Logic-Gate-Extraction are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open multiple patterning framework☆85May 17, 2024Updated last year
- Machine Generated Analog IC Layout☆282Apr 24, 2024Updated last year
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Aug 19, 2024Updated last year
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆83Jul 10, 2025Updated 9 months ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Circuit release of the MAGICAL project☆40Jan 10, 2020Updated 6 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆92Apr 30, 2025Updated 11 months ago
- This repository contains source code that is aimed at converting a Spice NetList to its corresponding layout.☆26Mar 29, 2021Updated 5 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Tries in C++☆13Aug 20, 2020Updated 5 years ago
- ☆33Dec 16, 2021Updated 4 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 4 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆130Apr 23, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆44Jan 26, 2020Updated 6 years ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆50Mar 17, 2026Updated last month
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆195May 19, 2025Updated 11 months ago
- Tool for parsing an integrated circuit test file from STIL to the particular file format of a Teradyne tester.☆15May 17, 2018Updated 7 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆139Jul 20, 2024Updated last year
- ☆13Aug 6, 2022Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- SPICE based IBIS simulation☆17Jan 2, 2025Updated last year
- ☆21Nov 29, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- ☆108Apr 10, 2026Updated last week
- Implementation of paper "D2Match: Leveraging Deep Learning and Degeneracy for Subgraph Matching"☆13Dec 30, 2023Updated 2 years ago
- Generative AI for Semiconductor Design: Engineering Assistant built with Bedrock, Knowledge Bases and Langchain☆28Jun 14, 2024Updated last year
- Convert C files into Verilog☆21Jan 27, 2019Updated 7 years ago
- Database and Tool Framework for EDA☆125Jan 25, 2021Updated 5 years ago
- How to correctly write a flicker-noise model for RF simulation.☆25Sep 19, 2025Updated 6 months ago
- ☆80Oct 29, 2025Updated 5 months ago
- ☆352Jan 13, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Arbitrary Cell Generator enables parametrized grid-free circuit layout creation☆17Jun 1, 2020Updated 5 years ago
- Open source hardware down to the chip level!☆30Sep 24, 2021Updated 4 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- Deep learning toolkit-enabled VLSI placement☆974Feb 19, 2026Updated last month
- Code for paper: Neural Architecture Search in Graph Neural Networks (BRACIS 2020)☆19Jul 6, 2023Updated 2 years ago
- Summer School Week 1 & 2 repo☆12Jul 1, 2022Updated 3 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago