rachelselinar / ReGDS-Logic-Gate-ExtractionLinks
A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
☆31Updated last year
Alternatives and similar repositories for ReGDS-Logic-Gate-Extraction
Users that are interested in ReGDS-Logic-Gate-Extraction are comparing it to the libraries listed below
Sorting:
- EDA physical synthesis optimization kit☆62Updated last year
- EDA wiki☆53Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 6 months ago
- ☆44Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- ☆106Updated 5 years ago
- Open source process design kit for 28nm open process☆66Updated last year
- An open multiple patterning framework☆79Updated last year
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆33Updated 5 years ago
- A LEF/DEF Utility.☆32Updated 6 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 2 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- ILP SAT Detailed Router☆12Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- Library of open source Process Design Kits (PDKs)☆56Updated 2 weeks ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- An infrastructure for integrated EDA☆41Updated 2 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- Delay Calculation ToolKit☆32Updated 3 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- Database and Tool Framework for EDA☆118Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆65Updated last week
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆127Updated 2 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- ☆77Updated 4 months ago
- DATC RDF☆50Updated 5 years ago
- IDEA project source files☆108Updated 2 weeks ago
- ☆35Updated 2 years ago