A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.
☆37Aug 21, 2024Updated 2 years ago
Alternatives and similar repositories for ReGDS-Logic-Gate-Extraction
Users that are interested in ReGDS-Logic-Gate-Extraction are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open multiple patterning framework☆87May 17, 2024Updated 2 years ago
- ☆13Jul 3, 2020Updated 6 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Jun 6, 2019Updated 7 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 5 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆103Apr 30, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆10Feb 8, 2023Updated 3 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 6 years ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆96Jul 10, 2025Updated last year
- Analog IC symmetry extraction benchmark of AncstrGNN☆11Aug 19, 2024Updated 2 years ago
- DATC Robust Design Flow.☆37Jan 21, 2020Updated 6 years ago
- Circuit release of the MAGICAL project☆40Jan 10, 2020Updated 6 years ago
- Optimization results for superconducting electronic (SCE) circuits☆19Dec 5, 2023Updated 2 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆199May 19, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆44Jan 26, 2020Updated 6 years ago
- A ROHD-based framework for connectivity and assembly of hardware designs.☆14Sep 9, 2026Updated last month
- This repository contains source code that is aimed at converting a Spice NetList to its corresponding layout.☆28Mar 29, 2021Updated 5 years ago
- ☆34Dec 16, 2021Updated 4 years ago
- Tries in C++☆14Aug 20, 2020Updated 6 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆143Jul 20, 2024Updated 2 years ago
- ☆18May 1, 2024Updated 2 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆139Apr 23, 2023Updated 3 years ago
- Verilog-A implementation of MOSFET model BSIM4.8☆16Oct 4, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Polyhedral Compilation tool for High Level Synthesis.☆11May 13, 2014Updated 12 years ago
- 📸 ADCs for faster image sensors☆13Updated this week
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆116Mar 9, 2024Updated 2 years ago
- BaseJump Open-Source Hardware Accelerator Packages and Sockets☆12Jul 7, 2025Updated last year
- ☆133Updated this week
- This repo contains the source code and pretrained model for the paper "Semi-Supervised Hotspot Detection with Self-Paced Multi-Task Lear…☆16Oct 18, 2018Updated 8 years ago
- Using the floating random walk method to extract the inter-connect capacitance in the VLSI☆12May 23, 2019Updated 7 years ago
- ROHD Wave Viewer is a waveform viewer Flutter app, part of the ROHD ecosystem. It works in-browser, integrated as a Flutter widget, used …☆14Oct 25, 2026Updated last week
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆153Jul 23, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆153Mar 20, 2023Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 9 years ago
- ☆14Aug 6, 2022Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆166Feb 27, 2023Updated 3 years ago
- Dual RISC-V DISC with integrated eFPGA☆18Oct 9, 2021Updated 5 years ago
- ☆22Nov 29, 2022Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago