RsynTeam / rsyn-x

Related projects ⓘ

Alternatives and complementary repositories for rsyn-x

• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆121Updated last year
• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆99Updated 4 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆147Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆97Updated 8 months ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆128Updated last year
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• ABKGroup / TritonRoute-WXL
  ☆25Updated 4 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆79Updated 3 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• cuhk-eda / cu-gr-2
  ☆35Updated 10 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆215Updated 4 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆68Updated 4 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆98Updated last week
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆34Updated 4 years ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆116Updated last month
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆46Updated 4 months ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆89Updated 4 years ago
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆33Updated 8 months ago
• tsung-wei-huang / ece5960-physical-design
  ☆36Updated last year
• asyncvlsi / lefdef
  Mirror of the Si2 LEF/DEF parser (v5.8)
  ☆12Updated 3 years ago
• nbulsi / also
  A logic synthesis tool
  ☆68Updated 2 years ago
• mgwoo / RePlAce
  ☆10Updated 2 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆36Updated last month