Alternatives and similar repositories for libblifparse

Users that are interested in libblifparse are comparing it to the libraries listed below

• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• verilog-to-routing / libsdcparse
  ☆12Updated 5 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 10 years ago
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆52Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 9 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last week
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last week
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆33Updated 9 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 3 weeks ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆49Updated 4 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆50Updated 4 years ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated 2 months ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆101Updated 3 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆50Updated 3 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆48Updated 2 years ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago