chipsalliance / fpga-interchange-schemaView external linksLinks
☆59Jul 4, 2022Updated 3 years ago
Alternatives and similar repositories for fpga-interchange-schema
Users that are interested in fpga-interchange-schema are comparing it to the libraries listed below
Sorting:
- Python interface to FPGA interchange format☆41Oct 19, 2022Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆35Jun 3, 2025Updated 8 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆47Updated this week
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Jan 22, 2026Updated 3 weeks ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆15Mar 1, 2022Updated 3 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆18Jun 16, 2022Updated 3 years ago
- FPGA tool performance profiling☆105Feb 24, 2024Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated this week
- ☆17Aug 16, 2023Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Apr 30, 2025Updated 9 months ago
- Xilinx Unisim Library in Verilog☆86Jul 22, 2020Updated 5 years ago
- Block-diagram style digital logic visualizer☆23Sep 16, 2015Updated 10 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆120Oct 3, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- ☆20May 8, 2012Updated 13 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Dec 20, 2022Updated 3 years ago
- Intel Compiler for SystemC☆27Jun 1, 2023Updated 2 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- Netlist and Verilog Haskell Package☆18Nov 21, 2010Updated 15 years ago
- VUnit and Cocotb Smashed Together☆15May 31, 2024Updated last year
- Standard and Curated cores, tested and working.☆11Dec 29, 2022Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Aug 20, 2022Updated 3 years ago
- FOSS Flow For FPGA☆423Jan 6, 2025Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Jul 22, 2021Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Hybrid Threading Tool Set☆15Sep 24, 2020Updated 5 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated last year
- ☆28Feb 21, 2018Updated 7 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- ☆17Nov 18, 2025Updated 2 months ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆14Updated this week
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆283Mar 27, 2024Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆65Dec 5, 2025Updated 2 months ago