UIUC-ChenLab / NimblockLinks
☆13Updated 2 years ago
Alternatives and similar repositories for Nimblock
Users that are interested in Nimblock are comparing it to the libraries listed below
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆32Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆62Updated 10 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- MICRO22 artifact evaluation for Sparseloop☆47Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- ☆42Updated last year
- An integrated CGRA design framework☆91Updated 10 months ago
- Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"☆33Updated last year
- ☆29Updated 4 years ago
- ☆56Updated 2 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 3 months ago
- A list of our chiplet simulaters☆47Updated 7 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆61Updated 4 years ago
- ☆72Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆71Updated 4 months ago
- ☆10Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 8 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆70Updated last month
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago