Alternatives and similar repositories for Nimblock

Users that are interested in Nimblock are comparing it to the libraries listed below

• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 9 months ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆21Updated 9 months ago
• hngenc / stellar
  ☆32Updated last year
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 4 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• ucb-bar / MoCA
  ☆28Updated 2 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• he-actlab / planaria.code
  ☆29Updated 4 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆70Updated 3 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆46Updated 3 years ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆46Updated 2 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆68Updated 2 weeks ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆24Updated 7 months ago
• maestro-project / gamma
  ☆42Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆73Updated 3 weeks ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆73Updated last year
• CMU-SAFARI / Sectored-DRAM
  A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…
  ☆12Updated last year
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆22Updated last year
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆85Updated 6 years ago
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆53Updated 5 months ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆85Updated 2 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• scalesim-project / scale-sim-v3
  ☆54Updated last month
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year