Alternatives and similar repositories for hipr

Users that are interested in hipr are comparing it to the libraries listed below

• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆43Updated last week
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆62Updated 3 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆65Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆73Updated last month
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated last month
• StanfordAHA / aha
  ☆62Updated this week
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆44Updated last year
• wincle626 / HLS_Legup
  ☆29Updated 8 years ago
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆83Updated 7 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆127Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• lana555 / dynamatic
  ☆87Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆128Updated 3 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• microsoft / brainsmith
  Open-source AI acceleration on FPGA: from ONNX to RTL
  ☆48Updated last month
• Xilinx / merlin-compiler
  ☆60Updated 2 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆55Updated 6 years ago
• cornell-zhang / rosetta
  Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)
  ☆169Updated 2 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆62Updated 7 months ago
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis (ICCAD'25)
  ☆32Updated this week
• tancheng / CGRA-Bench
  ☆14Updated last week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 10 months ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆70Updated 2 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago