icgrp / hipr
☆13Updated last year
Related projects ⓘ
Alternatives and complementary repositories for hipr
- DASS HLS Compiler☆27Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- A hardware synthesis framework with multi-level paradigm☆37Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- A tool to generate optimized hardware files for univariate functions.☆21Updated 7 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- CGRA framework with vectorization support.☆19Updated this week
- ILA Model Database☆20Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- ☆87Updated 8 months ago
- ☆14Updated 2 years ago
- ☆10Updated last year
- ☆26Updated 7 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆21Updated last month
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- ☆57Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- A fast, accurate trace-based simulator for High-Level Synthesis.☆36Updated 6 months ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆57Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆30Updated this week
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- ☆22Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆22Updated 2 months ago
- ☆27Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated last month