Pin-Accessible Legalization for Mixed-Cell-Height Circuits
☆32Feb 25, 2022Updated 4 years ago
Alternatives and similar repositories for ripple
Users that are interested in ripple are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RePlAce global placement tool☆254Aug 13, 2020Updated 5 years ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆43Sep 7, 2025Updated 9 months ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆19Oct 8, 2021Updated 4 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆167Jun 26, 2026Updated last week
- CUGR, VLSI Global Routing Tool Developed by CUHK☆150Feb 27, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆14Jul 19, 2024Updated last year
- ☆40Nov 3, 2020Updated 5 years ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 3 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆146Mar 20, 2023Updated 3 years ago
- A LEF/DEF Utility.☆34Aug 15, 2019Updated 6 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆14Mar 5, 2017Updated 9 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆93Feb 11, 2020Updated 6 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆97Apr 30, 2025Updated last year
- ☆63Mar 8, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆19Jan 20, 2023Updated 3 years ago
- UCSD Detailed Router☆98Jan 5, 2021Updated 5 years ago
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆25Feb 24, 2026Updated 4 months ago
- Database and Tool Framework for EDA☆126Jan 25, 2021Updated 5 years ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆25Feb 16, 2023Updated 3 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆61Aug 7, 2022Updated 3 years ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆62Apr 22, 2022Updated 4 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆197May 19, 2025Updated last year
- Applying Deep Q-learning for Global Routing☆132Sep 15, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆17Jul 16, 2020Updated 5 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆139Jul 20, 2024Updated last year
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 4 years ago
- Implementations of DeepPlace, PRNet, HubRouter, PreRoutGNN, FlexPlanner and DSBRouter.☆314Nov 23, 2025Updated 7 months ago
- Open Source Detailed Placement engine☆41Nov 27, 2019Updated 6 years ago
- Deep learning toolkit-enabled VLSI placement☆1,025Apr 24, 2026Updated 2 months ago
- Analog Placement Quality Prediction☆26Mar 24, 2023Updated 3 years ago
- 張耀文老師的"奈米積體電路實體設計"作業(Physical Design)☆11Jan 18, 2024Updated 2 years ago
- Implementation of several grid routers in Rust☆13Jun 16, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Design Rule Checker with GPU Acceleration☆65Sep 15, 2023Updated 2 years ago
- [FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs☆25Feb 14, 2023Updated 3 years ago
- 台大李宏毅老师机器学习课程☆10Apr 29, 2020Updated 6 years ago
- Boost.org graph_parallel module☆33Apr 22, 2026Updated 2 months ago
- A High-performance Timing Analysis Tool for VLSI Systems☆10Feb 11, 2021Updated 5 years ago
- A red-black self-balancing interval tree☆32Aug 6, 2020Updated 5 years ago
- DATC RDF☆49Jul 31, 2020Updated 5 years ago