cuhk-eda / ripple-fpga
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
☆89Updated 4 years ago
Alternatives and similar repositories for ripple-fpga:
Users that are interested in ripple-fpga are comparing it to the libraries listed below
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆56Updated 7 months ago
- IDEA project source files☆101Updated 2 months ago
- ☆101Updated 5 years ago
- DATC RDF☆49Updated 4 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆98Updated 10 months ago
- DATC Robust Design Flow.☆37Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆79Updated last week
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆53Updated 4 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆123Updated 5 months ago
- A Standalone Structural Verilog Parser☆86Updated 2 years ago
- UCSD Detailed Router☆82Updated 4 years ago
- ☆117Updated 6 months ago
- Collection of digital hardware modules & projects (benchmarks)☆36Updated 2 months ago
- ☆55Updated this week
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 2 years ago
- Global Router Built for ICCAD Contest 2019☆29Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆34Updated 2 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆54Updated 2 years ago
- Qrouter detail router for digital ASIC designs☆55Updated 3 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆150Updated 2 weeks ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆132Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆125Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 2 months ago
- Logic synthesis and ABC based optimization☆48Updated last month
- Introductory course into static timing analysis (STA).☆78Updated 2 months ago
- ☆32Updated 4 years ago
- EDA physical synthesis optimization kit☆50Updated last year
- Database and Tool Framework for EDA☆108Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆155Updated 4 years ago