cuhk-eda / ripple-fpgaLinks
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
☆90Updated 5 years ago
Alternatives and similar repositories for ripple-fpga
Users that are interested in ripple-fpga are comparing it to the libraries listed below
Sorting:
- ☆108Updated 6 years ago
- IDEA project source files☆111Updated 2 months ago
- UCSD Detailed Router☆94Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆59Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆108Updated last year
- DATC Robust Design Flow.☆36Updated 5 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Updated 8 months ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- DATC RDF☆50Updated 5 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆136Updated last year
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 3 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆141Updated 2 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- Global Router Built for ICCAD Contest 2019☆33Updated 5 years ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- VLSI EDA Global Router☆79Updated 7 years ago
- Open Source Detailed Placement engine☆40Updated 6 years ago
- OpenDesign Flow Database☆17Updated 7 years ago
- ☆77Updated this week
- CUGR, VLSI Global Routing Tool Developed by CUHK☆141Updated 2 years ago
- A logic synthesis tool☆84Updated 4 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆98Updated this week
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Updated 3 years ago
- EDA physical synthesis optimization kit☆64Updated 2 years ago
- GPU-based logic synthesis tool☆97Updated last month
- Database and Tool Framework for EDA☆122Updated 4 years ago