cpc / openasipLinks
Open Application-Specific Instruction Set processor tools (OpenASIP)
☆168Updated last week
Alternatives and similar repositories for openasip
Users that are interested in openasip are comparing it to the libraries listed below
Sorting:
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- The Task Parallel System Composer (TaPaSCo)☆114Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 2 months ago
- ☆104Updated 3 years ago
- Next generation CGRA generator☆116Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- Algorithmic C Datatypes☆133Updated 3 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated 3 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆229Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- FPGA tool performance profiling☆103Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated 2 years ago
- ☆150Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- high-performance RTL simulator☆184Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆287Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆58Updated 3 years ago
- Main page☆128Updated 5 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago