cpc / openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
☆153Updated last week
Alternatives and similar repositories for openasip:
Users that are interested in openasip are comparing it to the libraries listed below
- An open source high level synthesis (HLS) tool built on top of LLVM☆120Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆250Updated last month
- ☆102Updated 2 years ago
- Next generation CGRA generator☆111Updated last week
- FPGA tool performance profiling☆102Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆173Updated 9 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 6 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆225Updated 5 months ago
- The Task Parallel System Composer (TaPaSCo)☆108Updated 3 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆266Updated 5 months ago
- Fabric generator and CAD tools☆176Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- high-performance RTL simulator☆156Updated 10 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆61Updated 11 months ago
- ☆131Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆221Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- PACoGen: Posit Arithmetic Core Generator☆69Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆95Updated last month
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- A Fast, Low-Overhead On-chip Network☆195Updated 2 weeks ago
- Verilog Configurable Cache☆175Updated 4 months ago
- The multi-core cluster of a PULP system.☆89Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆145Updated last month
- ☆86Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- FPGA Assembly (FASM) Parser and Generator☆91Updated 2 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆277Updated this week