Open Application-Specific Instruction Set processor tools (OpenASIP)
☆185Mar 13, 2026Updated 3 months ago
Alternatives and similar repositories for openasip
Users that are interested in openasip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Scalable Interface for RISC-V ISA Extensions☆26Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 11 months ago
- The Task Parallel System Composer (TaPaSCo)☆126Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆230Nov 22, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Dec 17, 2025Updated 5 months ago
- Example for running IREE in a bare-metal Arm environment.☆43Feb 24, 2026Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆159Updated this week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆255Jun 5, 2026Updated last week
- ☆246Aug 12, 2022Updated 3 years ago
- Open-source FPGA research and prototyping framework.☆211Aug 8, 2024Updated last year
- A Rocket-based RISC-V superscalar in-order core☆40Mar 11, 2026Updated 3 months ago
- ☆23Mar 28, 2023Updated 3 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A Linux-capable RISC-V multicore for and by the world☆811Jun 5, 2026Updated last week
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 6 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆544Updated this week
- design and verification of asynchronous circuits☆51Apr 26, 2026Updated last month
- ☆33Jan 7, 2025Updated last year
- ☆11Dec 18, 2017Updated 8 years ago
- The OpenPiton Platform☆31May 22, 2023Updated 3 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆524Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Constrained RAndom Verification Enviroment (CRAVE)☆19Nov 23, 2023Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆66May 29, 2025Updated last year
- An open silicon CHERIoT Ibex microcontroller chip☆18May 23, 2025Updated last year
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆308May 19, 2026Updated 3 weeks ago
- Basic Common Modules☆48Jun 5, 2026Updated last week
- SystemVerilog file list pruner☆19Mar 2, 2026Updated 3 months ago
- high-performance RTL simulator☆193Jun 19, 2024Updated last year
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆413May 29, 2026Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆294Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆18Jan 15, 2026Updated 4 months ago
- Bluespec Compiler (BSC)☆1,114May 15, 2026Updated 3 weeks ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,824Mar 25, 2026Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆613May 26, 2026Updated 2 weeks ago
- 高级计算机体系结构记分牌算法实验☆13Dec 22, 2018Updated 7 years ago
- SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of…☆11Jul 19, 2018Updated 7 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago