cpc / openasipLinks
Open Application-Specific Instruction Set processor tools (OpenASIP)
☆170Updated last week
Alternatives and similar repositories for openasip
Users that are interested in openasip are comparing it to the libraries listed below
Sorting:
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆230Updated this week
- The Task Parallel System Composer (TaPaSCo)☆115Updated last week
- Algorithmic C Datatypes☆133Updated last month
- ☆104Updated 3 years ago
- Next generation CGRA generator☆118Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 7 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last month
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- high-performance RTL simulator☆184Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- FPGA tool performance profiling☆104Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆275Updated 3 months ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆236Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆227Updated 2 years ago
- ☆59Updated 3 years ago
- ☆150Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Chisel components for FPGA projects☆128Updated 2 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆220Updated last week
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆288Updated 2 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆206Updated 2 weeks ago