Alternatives and similar repositories for bender

Users that are interested in bender are comparing it to the libraries listed below

• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆318Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆218Updated this week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆439Updated 2 months ago
• dalance / svlint
  SystemVerilog linter
  ☆343Updated last month
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆390Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 3 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆179Updated 3 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 5 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆614Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆275Updated 2 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆252Updated 3 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆235Updated 6 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆131Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆190Updated 2 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆253Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆386Updated 4 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 5 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆255Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated 2 weeks ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• SpinalHDL / NaxRiscv
  ☆284Updated 2 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆381Updated 2 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆211Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆529Updated last week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆223Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆201Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆136Updated last month
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆174Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆573Updated this week