A dependency management tool for hardware projects.
☆354Mar 12, 2026Updated last week
Alternatives and similar repositories for bender
Users that are interested in bender are comparing it to the libraries listed below
Sorting:
- A SystemVerilog source file pickler.☆60Oct 20, 2024Updated last year
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆465Nov 4, 2025Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆272Mar 13, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,519Mar 11, 2026Updated last week
- Common SystemVerilog components☆723Mar 11, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,789Mar 13, 2026Updated last week
- ☆33Jan 7, 2025Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆252Feb 22, 2026Updated 3 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆451Mar 8, 2026Updated last week
- SystemVerilog synthesis tool☆229Mar 10, 2025Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- SystemVerilog compiler and language services☆985Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆653Jan 19, 2026Updated 2 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆315Feb 11, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,797Feb 17, 2026Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆202Mar 6, 2026Updated 2 weeks ago
- SystemVerilog linter☆378Nov 6, 2025Updated 4 months ago
- A hardware compiler based on LLHD and CIRCT☆266Jun 30, 2025Updated 8 months ago
- SystemVerilog file list pruner☆17Mar 2, 2026Updated 2 weeks ago
- Tools based upon slang for language server purpose☆22Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆314Mar 6, 2026Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆784Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 8 months ago
- ☆59Mar 31, 2025Updated 11 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆429Apr 20, 2022Updated 3 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆368Updated this week
- Control and status register code generator toolchain☆179Feb 27, 2026Updated 3 weeks ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Dec 27, 2020Updated 5 years ago
- cocotb: Python-based chip (RTL) verification☆2,284Mar 13, 2026Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆323Mar 13, 2026Updated last week
- SystemVerilog to Verilog conversion☆709Nov 24, 2025Updated 3 months ago
- lowRISC Style Guides☆487Nov 6, 2025Updated 4 months ago
- Modular hardware build system☆1,131Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆577Mar 11, 2026Updated last week
- whatever it means☆15Mar 13, 2026Updated last week
- SystemVerilog frontend for Yosys☆207Mar 13, 2026Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆211Updated this week