A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
☆329Oct 2, 2026Updated last week
Alternatives and similar repositories for mempool
Users that are interested in mempool are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 20, 2026Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆175Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆284Nov 6, 2024Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆230Nov 22, 2023Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆375Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated 2 months ago
- The multi-core cluster of a PULP system.☆119Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆642Sep 14, 2026Updated 3 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated last year
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆132Sep 7, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,714Sep 24, 2026Updated 2 weeks ago
- Common SystemVerilog components☆807Sep 18, 2026Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆689Sep 28, 2026Updated last week
- ☆27Jan 30, 2026Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,212Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆246Updated this week
- A Fast, Low-Overhead On-chip Network☆357Updated this week
- 32-bit Superscalar RISC-V CPU☆1,313Sep 18, 2021Updated 5 years ago
- A dependency management tool for hardware projects.☆395Oct 1, 2026Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆102Aug 20, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆551Updated this week
- A Linux-capable RISC-V multicore for and by the world☆835Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,150Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SERV - The SErial RISC-V CPU☆1,900Aug 25, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,309Oct 1, 2026Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆119Sep 12, 2026Updated 3 weeks ago
- The OpenPiton Platform☆832Feb 25, 2026Updated 7 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,087Updated this week
- GEMM and GEMM-Ops accelerator for PULP systems☆123Sep 30, 2026Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆115Sep 18, 2023Updated 3 years ago
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VeeR EH1 core☆971Jul 16, 2026Updated 2 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆728Sep 14, 2026Updated 3 weeks ago
- VeeR EL2 Core☆345Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,045Updated this week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆572Nov 26, 2024Updated last year
- ☆53Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆427Updated this week