pulp-platform / mempoolLinks
A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
☆310Updated this week
Alternatives and similar repositories for mempool
Users that are interested in mempool are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆296Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆273Updated last month
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated 11 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated last year
- ☆300Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆280Updated this week
- RISC-V soft-core microcontroller for FPGA implementation☆186Updated 3 weeks ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 5 months ago
- VeeR EL2 Core☆303Updated this week
- CORE-V Family of RISC-V Cores☆304Updated 9 months ago
- Instruction Set Generator initially contributed by Futurewei☆300Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- ☆247Updated 2 years ago
- Verilog Configurable Cache☆185Updated this week
- RISC-V Torture Test☆202Updated last year
- ☆147Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆539Updated 3 weeks ago
- RISC-V Processor Trace Specification☆195Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- RISC-V CPU Core☆393Updated 4 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆195Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- ☆354Updated 2 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆161Updated 3 years ago
- RISC-V System on Chip Template☆159Updated 2 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆280Updated this week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago