Alternatives and similar repositories for mempool

Users that are interested in mempool are comparing it to the libraries listed below

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆245Updated 11 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆286Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆266Updated last week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆227Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 4 months ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆183Updated 5 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• SpinalHDL / NaxRiscv
  ☆297Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆274Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆300Updated 7 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆183Updated 10 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆184Updated 2 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆325Updated 9 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆180Updated last week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆217Updated last week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated last month
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated this week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆415Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆163Updated 5 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆387Updated 3 months ago
• ucb-bar / berkeley-hardfloat
  ☆346Updated 3 weeks ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆158Updated 3 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago