A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
☆313Feb 11, 2026Updated 2 weeks ago
Alternatives and similar repositories for mempool
Users that are interested in mempool are comparing it to the libraries listed below
Sorting:
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆258Nov 6, 2024Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆138Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆570Oct 21, 2025Updated 4 months ago
- The multi-core cluster of a PULP system.☆111Feb 2, 2026Updated 3 weeks ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆318Feb 20, 2026Updated last week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- Common SystemVerilog components☆712Feb 6, 2026Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆268Feb 19, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,500Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆155Oct 31, 2024Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- Generic Register Interface (contains various adapters)☆136Feb 14, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,178Sep 18, 2021Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆196Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆490Nov 27, 2025Updated 3 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆119Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,149Feb 21, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,187May 26, 2025Updated 9 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆81Feb 5, 2026Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆769Feb 9, 2026Updated 2 weeks ago
- SERV - The SErial RISC-V CPU☆1,757Feb 19, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,817Feb 18, 2026Updated last week
- A dependency management tool for hardware projects.☆347Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆661Updated this week
- The OpenPiton Platform☆772Updated this week
- VeeR EH1 core☆927May 29, 2023Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,771Feb 17, 2026Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆99Feb 20, 2026Updated last week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆488Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆295Feb 4, 2026Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 8 months ago
- A SystemVerilog source file pickler.☆60Oct 20, 2024Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Sep 18, 2023Updated 2 years ago
- VeeR EL2 Core☆318Dec 29, 2025Updated last month
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆404Feb 6, 2026Updated 3 weeks ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Feb 20, 2026Updated last week
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆542Nov 26, 2024Updated last year
- Verilog Configurable Cache☆192Feb 17, 2026Updated last week