pulp-platform / mempoolLinks
A 256-RISC-V-core system with low-latency access into shared L1 memory.
☆303Updated last week
Alternatives and similar repositories for mempool
Users that are interested in mempool are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 9 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 9 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆278Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 3 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 9 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- RISC-V microcontroller IP core developed in Verilog☆178Updated 4 months ago
- Instruction Set Generator initially contributed by Futurewei☆293Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- CORE-V Family of RISC-V Cores☆289Updated 6 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- ☆243Updated 2 years ago
- ☆294Updated 2 weeks ago
- VeeR EL2 Core☆294Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆160Updated 5 years ago
- RISC-V CPU Core☆370Updated 2 months ago
- ☆148Updated last year
- Verilog Configurable Cache☆181Updated 8 months ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆275Updated this week
- RISC-V Processor Trace Specification☆192Updated 3 weeks ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆155Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆525Updated 2 weeks ago
- RISC-V System on Chip Template☆159Updated last week
- RISC-V Torture Test☆197Updated last year
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆404Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆176Updated this week
- ☆336Updated 11 months ago
- Ariane is a 6-stage RISC-V CPU☆142Updated 5 years ago