pulp-platform / mempoolLinks
A 256-RISC-V-core system with low-latency access into shared L1 memory.
☆298Updated last week
Alternatives and similar repositories for mempool
Users that are interested in mempool are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆237Updated 7 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆267Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆504Updated 4 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆214Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆258Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆288Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆225Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆261Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 7 months ago
- RISC-V microcontroller IP core developed in Verilog☆174Updated 2 months ago
- VeeR EL2 Core☆288Updated 2 weeks ago
- ☆238Updated 2 years ago
- CORE-V Family of RISC-V Cores☆274Updated 4 months ago
- RISC-V CPU Core☆337Updated 2 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆435Updated this week
- Verilog Configurable Cache☆178Updated 6 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆320Updated 6 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆559Updated 3 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆581Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆178Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- Common SystemVerilog components☆629Updated this week
- ☆179Updated last year
- ☆289Updated 3 months ago
- A Linux-capable RISC-V multicore for and by the world☆709Updated last month
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆268Updated this week
- ☆331Updated 9 months ago
- RISC-V Torture Test☆196Updated 11 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆214Updated 4 years ago
- Ariane is a 6-stage RISC-V CPU☆140Updated 5 years ago