pulp-platform / heroLinks
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
☆105Updated last year
Alternatives and similar repositories for hero
Users that are interested in hero are comparing it to the libraries listed below
Sorting:
- The multi-core cluster of a PULP system.☆101Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆102Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆165Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆101Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated this week
- ☆65Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆112Updated last week
- Pure digital components of a UCIe controller☆63Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆153Updated 2 years ago
- ☆59Updated 4 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆132Updated last week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated 2 weeks ago
- An energy-efficient RISC-V floating-point compute cluster.☆88Updated last week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆59Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- ☆96Updated last year
- ☆86Updated last year
- Next generation CGRA generator☆111Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆202Updated last month
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago