pulp-platform / heroLinks
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
☆112Updated 2 years ago
Alternatives and similar repositories for hero
Users that are interested in hero are comparing it to the libraries listed below
Sorting:
- ☆80Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆184Updated last month
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆109Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- The multi-core cluster of a PULP system.☆108Updated 3 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Next generation CGRA generator☆115Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆114Updated 3 weeks ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
- The Task Parallel System Composer (TaPaSCo)☆110Updated 5 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆86Updated 2 weeks ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Open source high performance IEEE-754 floating unit☆85Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- ☆59Updated last week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆92Updated 2 months ago
- Simple runtime for Pulp platforms☆49Updated 3 weeks ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Pure digital components of a UCIe controller☆74Updated 2 weeks ago
- RISC-V Matrix Specification☆22Updated 10 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 7 months ago