Alternatives and similar repositories for pulpissimo

Users that are interested in pulpissimo are comparing it to the libraries listed below

• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆511Updated 9 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆654Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆524Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆602Updated last month
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆590Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆587Updated 4 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆296Updated 2 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆275Updated 5 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆453Updated 2 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,112Updated 3 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆373Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆731Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆456Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆663Updated 2 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆450Updated 2 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,365Updated last week
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆372Updated last year
• ucb-bar / berkeley-hardfloat
  ☆341Updated last year
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆894Updated 2 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆670Updated 2 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆382Updated 2 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆729Updated 2 weeks ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆219Updated 5 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 9 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆342Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆509Updated 3 years ago