Alternatives and similar repositories for morty

Users that are interested in morty are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• chipsalliance / uvm-verilator
  ☆96Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 4 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 2 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆135Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆74Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆115Updated 3 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆104Updated last week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 9 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 2 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆64Updated 8 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆123Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆95Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆46Updated 9 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆69Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 2 weeks ago
• bsc-loca / sargantana
  ☆105Updated last month
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆86Updated last week
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆41Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆169Updated 3 weeks ago