Alternatives and similar repositories for morty

Users that are interested in morty are comparing it to the libraries listed below

• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆165Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆111Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 6 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆103Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆211Updated 6 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• pulp-platform / svase
  ☆32Updated 8 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 3 months ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆27Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated 3 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆233Updated 3 weeks ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• pulp-platform / cheshire-ihp130-o
  ☆53Updated 6 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆116Updated 3 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆46Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated 11 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago