Alternatives and similar repositories for morty:

Users that are interested in morty are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated 11 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• chipsalliance / uvm-verilator
  ☆92Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆44Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆100Updated last week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆57Updated 3 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 8 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆114Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆71Updated 2 weeks ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 7 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆62Updated 11 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆90Updated last week
• pulp-platform / cheshire-ihp130-o
  ☆37Updated last month
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆54Updated 3 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆113Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆38Updated 3 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆96Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆103Updated 3 years ago