pulp-platform / mortyLinks
A SystemVerilog source file pickler.
☆60Updated last year
Alternatives and similar repositories for morty
Users that are interested in morty are comparing it to the libraries listed below
Sorting:
- Determines the modules declared and instantiated in a SystemVerilog file☆49Updated last year
- Hardware generator debugger☆77Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- ☆113Updated 2 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- SystemVerilog frontend for Yosys☆187Updated this week
- FPGA tool performance profiling☆104Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- ☆31Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- SystemVerilog synthesis tool☆225Updated 10 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Test dashboard for verification features in Verilator☆28Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆145Updated last week
- ☆33Updated last year
- Generic Register Interface (contains various adapters)☆135Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆77Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- RISC-V Verification Interface☆136Updated last month
- ☆58Updated 9 months ago