pulp-platform / morty
A SystemVerilog source file pickler.
☆55Updated 4 months ago
Alternatives and similar repositories for morty:
Users that are interested in morty are comparing it to the libraries listed below
- AXI Adapter(s) for RISC-V Atomic Operations☆61Updated 6 months ago
- Hardware generator debugger☆73Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆43Updated 5 months ago
- SystemVerilog frontend for Yosys☆79Updated last week
- pulp_soc is the core building component of PULP based SoCs☆79Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- ☆88Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- ☆31Updated last year
- Generic Register Interface (contains various adapters)☆110Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆35Updated last month
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- ☆31Updated 2 months ago
- The multi-core cluster of a PULP system.☆80Updated last week
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆81Updated 5 months ago
- An automatic clock gating utility☆44Updated 7 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆74Updated 11 months ago
- RISC-V Verification Interface☆85Updated 3 weeks ago
- Mutation Cover with Yosys (MCY)☆80Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆57Updated this week
- ☆55Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- FPGA tool performance profiling☆102Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t …☆134Updated 2 weeks ago