pulp-platform / mortyLinks
A SystemVerilog source file pickler.
☆60Updated last year
Alternatives and similar repositories for morty
Users that are interested in morty are comparing it to the libraries listed below
Sorting:
- Determines the modules declared and instantiated in a SystemVerilog file☆51Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- ☆113Updated 2 months ago
- SystemVerilog frontend for Yosys☆194Updated last week
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Hardware generator debugger☆77Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated this week
- FPGA tool performance profiling☆105Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- SystemVerilog synthesis tool☆226Updated 10 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆246Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- RISC-V Verification Interface☆138Updated last week
- Test dashboard for verification features in Verilator☆29Updated this week
- ☆58Updated 10 months ago
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- ideas and eda software for vlsi design☆51Updated this week
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆34Updated 2 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated last year
- An automatic clock gating utility☆52Updated 9 months ago