A simple, basic, formally verified UART controller
☆336Jan 29, 2024Updated 2 years ago
Alternatives and similar repositories for wbuart32
Users that are interested in wbuart32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- Verilog UART☆561Feb 27, 2025Updated last year
- A small, light weight, RISC CPU soft core☆1,532Dec 8, 2025Updated 4 months ago
- Various HDL (Verilog) IP Cores☆895Jul 1, 2021Updated 4 years ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,566Apr 22, 2026Updated last week
- Bus bridges and other odds and ends☆663Mar 10, 2026Updated last month
- A utility for Composing FPGA designs from Peripherals☆188Dec 23, 2024Updated last year
- A wishbone controlled scope for FPGA's☆90Jan 12, 2024Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆116Apr 27, 2024Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆183Nov 10, 2021Updated 4 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆372Mar 15, 2026Updated last month
- An Open Source configuration of the Arty platform☆131Jan 17, 2024Updated 2 years ago
- Common SystemVerilog components☆738Apr 27, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog library for ASIC and FPGA designers☆1,410May 8, 2024Updated last year
- A collection of demonstration digital filters☆170Jan 18, 2024Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆317Sep 14, 2023Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆589Oct 10, 2021Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆308Apr 1, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆594Apr 20, 2026Updated 2 weeks ago
- Verilog PCI express components☆1,591Apr 26, 2024Updated 2 years ago
- Verilog I2C interface for FPGA implementation☆698Feb 27, 2025Updated last year
- Verilog AXI components for FPGA implementation☆2,030Feb 27, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆208Apr 8, 2026Updated 3 weeks ago
- RISC-V CPU Core☆426Jun 24, 2025Updated 10 months ago
- Opensource DDR3 Controller☆428Jan 18, 2026Updated 3 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆100Oct 31, 2022Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,133Feb 11, 2026Updated 2 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆448Feb 13, 2026Updated 2 months ago
- Verilog Ethernet components for FPGA implementation☆2,947Feb 27, 2025Updated last year
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆222May 21, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Small footprint and configurable PCIe core☆685Apr 27, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,410Feb 13, 2026Updated 2 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,127Jun 27, 2024Updated last year
- Collection of open-source peripherals in Verilog☆185May 3, 2022Updated 4 years ago
- Verilog AXI stream components for FPGA implementation☆886Feb 27, 2025Updated last year
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago