A simple, basic, formally verified UART controller
☆346Jan 29, 2024Updated 2 years ago
Alternatives and similar repositories for wbuart32
Users that are interested in wbuart32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wishbone controlled I2C controllers☆59Updated this week
- Verilog UART☆575Feb 27, 2025Updated last year
- A small, light weight, RISC CPU soft core☆1,573Dec 8, 2025Updated 8 months ago
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated last week
- Various HDL (Verilog) IP Cores☆930Jul 1, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,654Aug 5, 2026Updated last week
- Bus bridges and other odds and ends☆694Jun 2, 2026Updated 2 months ago
- A utility for Composing FPGA designs from Peripherals☆192Jul 4, 2026Updated last month
- A wishbone controlled scope for FPGA's☆93Jan 12, 2024Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆120Apr 27, 2024Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆193Nov 10, 2021Updated 4 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆398Updated this week
- An Open Source configuration of the Arty platform☆132Jan 17, 2024Updated 2 years ago
- Common SystemVerilog components☆781Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog library for ASIC and FPGA designers☆1,436May 8, 2024Updated 2 years ago
- A collection of demonstration digital filters☆179Jan 18, 2024Updated 2 years ago
- Must-have verilog systemverilog modules☆2,007Mar 12, 2026Updated 5 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆631Jul 24, 2026Updated 3 weeks ago
- A DDR3 memory controller in Verilog for various FPGAs☆623Oct 10, 2021Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆321Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆229Updated this week
- Verilog I2C interface for FPGA implementation☆716Feb 27, 2025Updated last year
- Verilog PCI express components☆1,642Apr 26, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verilog AXI components for FPGA implementation☆2,110Feb 27, 2025Updated last year
- Opensource DDR3 Controller☆470Jun 12, 2026Updated 2 months ago
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆103Oct 31, 2022Updated 3 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆343Sep 14, 2023Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆472Feb 13, 2026Updated 6 months ago
- 32-bit Superscalar RISC-V CPU☆1,289Sep 18, 2021Updated 4 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,220Feb 11, 2026Updated 6 months ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆223May 21, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Verilog Ethernet components for FPGA implementation☆3,064Feb 27, 2025Updated last year
- Small footprint and configurable PCIe core☆718Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,447Updated this week
- Collection of open-source peripherals in Verilog☆187May 3, 2022Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,328Jul 31, 2026Updated 2 weeks ago
- Verilog AXI stream components for FPGA implementation☆911Feb 27, 2025Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆71May 8, 2020Updated 6 years ago