ZipCPU / wbuart32
A simple, basic, formally verified UART controller
☆290Updated last year
Alternatives and similar repositories for wbuart32:
Users that are interested in wbuart32 are comparing it to the libraries listed below
- A full-speed device-side USB peripheral core written in Verilog.☆228Updated 2 years ago
- A simple RISC-V processor for use in FPGA designs.☆269Updated 6 months ago
- Bus bridges and other odds and ends☆523Updated last month
- Verilog UART☆146Updated 11 years ago
- RISC-V CPU Core☆317Updated 9 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆421Updated 3 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆250Updated 2 months ago
- Opensource DDR3 Controller☆276Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 11 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated last week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆312Updated 10 months ago
- Basic RISC-V Test SoC☆114Updated 5 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆418Updated 5 months ago
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- Small footprint and configurable DRAM core☆395Updated 2 months ago
- A utility for Composing FPGA designs from Peripherals☆171Updated 2 months ago
- Verilog digital signal processing components☆129Updated 2 years ago
- SystemVerilog to Verilog conversion☆598Updated 2 weeks ago
- Verilog SDRAM memory controller☆319Updated 7 years ago
- Common SystemVerilog components☆583Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- A simple implementation of a UART modem in Verilog.☆121Updated 3 years ago
- Example LED blinking project for your FPGA dev board of choice☆171Updated 2 weeks ago
- A huge VHDL library for FPGA development☆378Updated this week
- A Video display simulator☆162Updated 7 months ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆242Updated 5 years ago
- Verilog UART☆455Updated last week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆276Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆246Updated 4 months ago