A simple, basic, formally verified UART controller
☆343Jan 29, 2024Updated 2 years ago
Alternatives and similar repositories for wbuart32
Users that are interested in wbuart32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wishbone controlled I2C controllers☆58Jul 15, 2026Updated last week
- Verilog UART☆574Feb 27, 2025Updated last year
- A small, light weight, RISC CPU soft core☆1,568Dec 8, 2025Updated 7 months ago
- Generic Register Interface (contains various adapters)☆141Updated this week
- Various HDL (Verilog) IP Cores☆925Jul 1, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,631Updated this week
- Bus bridges and other odds and ends☆688Jun 2, 2026Updated last month
- A utility for Composing FPGA designs from Peripherals☆192Jul 4, 2026Updated 3 weeks ago
- A wishbone controlled scope for FPGA's☆93Jan 12, 2024Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆120Apr 27, 2024Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆192Nov 10, 2021Updated 4 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆393Jul 15, 2026Updated last week
- An Open Source configuration of the Arty platform☆132Jan 17, 2024Updated 2 years ago
- Common SystemVerilog components☆768Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog library for ASIC and FPGA designers☆1,435May 8, 2024Updated 2 years ago
- A collection of demonstration digital filters☆179Jan 18, 2024Updated 2 years ago
- Must-have verilog systemverilog modules☆1,998Mar 12, 2026Updated 4 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆624Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆617Oct 10, 2021Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆316Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆225Jul 14, 2026Updated last week
- Verilog I2C interface for FPGA implementation☆710Feb 27, 2025Updated last year
- Verilog PCI express components☆1,628Apr 26, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Verilog AXI components for FPGA implementation☆2,097Feb 27, 2025Updated last year
- Opensource DDR3 Controller☆463Jun 12, 2026Updated last month
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆103Oct 31, 2022Updated 3 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆338Sep 14, 2023Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆467Feb 13, 2026Updated 5 months ago
- 32-bit Superscalar RISC-V CPU☆1,283Sep 18, 2021Updated 4 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,201Feb 11, 2026Updated 5 months ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆222May 21, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verilog Ethernet components for FPGA implementation☆3,040Feb 27, 2025Updated last year
- Small footprint and configurable PCIe core☆714Jul 14, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,440Jul 2, 2026Updated 3 weeks ago
- Collection of open-source peripherals in Verilog☆186May 3, 2022Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,280Jun 27, 2024Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆906Feb 27, 2025Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆70May 8, 2020Updated 6 years ago