Alternatives and similar repositories for jtag_pulp

Users that are interested in jtag_pulp are comparing it to the libraries listed below

• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆11Updated 4 years ago
• AsFigo / MathLib
  MathLib DAC 2023 version
  ☆12Updated last year
• pulp-platform / axi_llc
  ☆30Updated last week
• open-dv / dma_axi
  ☆16Updated 6 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆23Updated last year
• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 11 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 8 months ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 4 months ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆53Updated last year
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 9 years ago
• pulp-platform / apb
  APB Logic
  ☆18Updated 7 months ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆19Updated 10 months ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated last month
• ljgibbslf / basic_cache_core
  ☆29Updated 4 years ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 2 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 5 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆45Updated 3 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆29Updated 6 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆28Updated 7 years ago
• briandong / regModel
  This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
  ☆12Updated 7 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 6 months ago