pulp-platform / jtag_pulp
☆12Updated last year
Alternatives and similar repositories for jtag_pulp:
Users that are interested in jtag_pulp are comparing it to the libraries listed below
- ☆16Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ☆19Updated 5 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- MathLib DAC 2023 version☆12Updated last year
- MMC (and derivative standards) host controller☆23Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- ☆24Updated 3 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆22Updated last month
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- APB Logic☆15Updated 3 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆11Updated last month
- ☆12Updated last month
- ☆21Updated 5 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Simple single-port AXI memory interface☆39Updated 9 months ago
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆21Updated 6 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago