pulp-platform / dram_rtl_simLinks
☆17Updated 3 months ago
Alternatives and similar repositories for dram_rtl_sim
Users that are interested in dram_rtl_sim are comparing it to the libraries listed below
Sorting:
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Updated last year
- ☆42Updated 9 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated 3 weeks ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- ☆32Updated last year
- A Toy-Purpose TPU Simulator☆21Updated last year
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- ☆29Updated 6 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆19Updated 8 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆17Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆47Updated 7 months ago
- ☆36Updated 4 years ago
- ☆29Updated last year
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 weeks ago
- A Heterogeneous GPU Platform for Chipyard SoC☆41Updated this week
- ☆38Updated 2 months ago
- DASS HLS Compiler☆29Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆78Updated last month
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆45Updated 9 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- ☆13Updated 2 years ago