☆19Oct 7, 2025Updated 5 months ago
Alternatives and similar repositories for dram_rtl_sim
Users that are interested in dram_rtl_sim are comparing it to the libraries listed below
Sorting:
- ☆21Mar 11, 2026Updated last week
- ☆82Feb 2, 2026Updated last month
- ☆13May 5, 2023Updated 2 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- Repo for PyChart 1.39, refs http://download.gna.org/pychart/☆10Sep 29, 2014Updated 11 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- ☆34Feb 17, 2026Updated last month
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Mar 20, 2025Updated last year
- ☆13May 8, 2025Updated 10 months ago
- CASS: Nvidia to AMD Transpilation with Data, Models, and Benchmark☆34Jun 24, 2025Updated 8 months ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 9 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- Arrow Matrix Decomposition - Communication-Efficient Distributed Sparse Matrix Multiplication☆15Mar 25, 2024Updated last year
- MICRO 2024 Evaluation Artifact for FuseMax☆16Aug 26, 2024Updated last year
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Mar 3, 2026Updated 2 weeks ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- ☆17Mar 26, 2025Updated 11 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Nov 12, 2025Updated 4 months ago
- The wafer-native AI accelerator simulation platform and inference engine.☆52Jan 1, 2026Updated 2 months ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Open source RTL simulation acceleration on commodity hardware☆34Apr 13, 2023Updated 2 years ago
- ☆14Mar 7, 2022Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- ☆67Apr 22, 2025Updated 10 months ago
- ☆38Updated this week
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆344Mar 9, 2026Updated last week
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆34Feb 11, 2026Updated last month
- Spike with a coherence supported cache model☆14Jul 9, 2024Updated last year
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 6 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Sep 18, 2023Updated 2 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- RISC-V IOMMU Demo (Linux & Bao)☆24Dec 5, 2023Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year