pulp-platform / dram_rtl_sim
☆12Updated 8 months ago
Alternatives and similar repositories for dram_rtl_sim
Users that are interested in dram_rtl_sim are comparing it to the libraries listed below
Sorting:
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆13Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated this week
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆20Updated 3 years ago
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Network on Chip for MPSoC☆26Updated this week
- ☆27Updated last month
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆27Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- ☆25Updated last year
- ☆27Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆35Updated 4 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated this week
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 8 months ago
- Spike with a coherence supported cache model☆13Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆17Updated this week
- ☆35Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- CNN accelerator☆27Updated 7 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 10 years ago