lowRISC / lowrisc-toolchains
UNSUPPORTED INTERNAL toolchain builds
☆33Updated 4 months ago
Alternatives and similar repositories for lowrisc-toolchains:
Users that are interested in lowrisc-toolchains are comparing it to the libraries listed below
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- The multi-core cluster of a PULP system.☆69Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- Generic Register Interface (contains various adapters)☆107Updated 4 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- FPGA reference design for the the Swerv EH1 Core☆70Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Announcements related to Verilator☆39Updated 4 years ago
- ☆87Updated last year
- FuseSoC standard core library☆126Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 7 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆63Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- ☆59Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ☆45Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆78Updated 3 years ago
- RISC-V RV32IMAFC Core for MCU☆36Updated 2 weeks ago
- RISC-V Verification Interface☆84Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆44Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago