Simple single-port AXI memory interface
☆50Jun 7, 2024Updated 2 years ago
Alternatives and similar repositories for axi_mem_if
Users that are interested in axi_mem_if are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 5 months ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Generic Register Interface (contains various adapters)☆140Updated this week
- ☆13May 5, 2023Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,607Jun 26, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated this week
- USB -> AXI Debug Bridge☆45Jun 5, 2021Updated 5 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Jun 1, 2026Updated last month
- APB Logic☆26Updated this week
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 4 years ago
- Common SystemVerilog components☆764Updated this week
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Jul 10, 2019Updated 6 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆92Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- Modular Multi-ported SRAM-based Memory☆33Nov 8, 2024Updated last year
- ☆63Feb 18, 2019Updated 7 years ago
- Verilog hardware abstraction library☆54Jun 26, 2026Updated last week
- UART -> AXI Bridge☆76Jul 1, 2021Updated 5 years ago
- ☆17Mar 21, 2026Updated 3 months ago
- AMBA AXI VIP☆468Jun 28, 2024Updated 2 years ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated last year
- ☆12Jul 20, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Interconnect Prototyping Assistant (IPA) is an interconnect modeling and generation framework built atop [MatchLib] (https://github.com/N…☆15Aug 20, 2024Updated last year
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated 2 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆46Oct 13, 2023Updated 2 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 13 years ago
- ☆25Oct 8, 2019Updated 6 years ago
- A simulator integrates ChampSim and Ramulator.☆23Jun 20, 2026Updated 2 weeks ago
- ☆52Jan 9, 2026Updated 5 months ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆23Mar 15, 2025Updated last year
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- ☆43Jan 14, 2022Updated 4 years ago
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 4 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- Mini CPU design with JTAG UART support☆21Jun 8, 2021Updated 5 years ago
- AXI DMA 32 / 64 bits☆129Jul 17, 2014Updated 11 years ago