pulp-platform / axi_mem_ifLinks
Simple single-port AXI memory interface
☆49Updated last year
Alternatives and similar repositories for axi_mem_if
Users that are interested in axi_mem_if are comparing it to the libraries listed below
Sorting:
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- General Purpose AXI Direct Memory Access☆62Updated last year
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- round robin arbiter☆78Updated 11 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- ☆40Updated 2 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated last week
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆58Updated 6 years ago
- Platform Level Interrupt Controller☆44Updated last year
- ☆114Updated 3 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Updated last week
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆33Updated 2 months ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- SoC Based on ARM Cortex-M3☆37Updated 8 months ago
- ☆70Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- AHB DMA 32 / 64 bits☆59Updated 11 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- ☆22Updated 5 years ago
- Modular Multi-ported SRAM-based Memory☆31Updated last year
- [UNRELEASED] FP div/sqrt unit for transprecision☆25Updated 5 months ago
- A Verilog implementation of a processor cache.☆35Updated 8 years ago
- APB Logic☆23Updated 2 weeks ago
- AXI4 BFM in Verilog☆35Updated 9 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago