pulp-platform / axi_riscv_atomicsLinks
AXI Adapter(s) for RISC-V Atomic Operations
☆64Updated last month
Alternatives and similar repositories for axi_riscv_atomics
Users that are interested in axi_riscv_atomics are comparing it to the libraries listed below
Sorting:
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- ☆96Updated last year
- Generic Register Interface (contains various adapters)☆121Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- The multi-core cluster of a PULP system.☆101Updated this week
- Platform Level Interrupt Controller☆41Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated this week
- ☆59Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆48Updated 5 months ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Pure digital components of a UCIe controller☆63Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- RISC-V Verification Interface☆94Updated 3 weeks ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- Simple single-port AXI memory interface☆41Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆165Updated this week
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- An Open-Source Design and Verification Environment for RISC-V☆83Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated this week
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago