pulp-platform / axi_riscv_atomicsLinks
AXI Adapter(s) for RISC-V Atomic Operations
☆66Updated last month
Alternatives and similar repositories for axi_riscv_atomics
Users that are interested in axi_riscv_atomics are comparing it to the libraries listed below
Sorting:
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- Generic Register Interface (contains various adapters)☆133Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- The multi-core cluster of a PULP system.☆109Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- ☆110Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- RISC-V Verification Interface☆126Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆125Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆117Updated 4 years ago
- An Open-Source Design and Verification Environment for RISC-V☆85Updated 4 years ago
- Simple single-port AXI memory interface☆47Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 9 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆88Updated last week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Platform Level Interrupt Controller☆44Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- A dynamic verification library for Chisel.☆158Updated last year