Alternatives and similar repositories for culsans

Users that are interested in culsans are comparing it to the libraries listed below

• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 5 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆96Updated this week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆26Updated 3 weeks ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆42Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆104Updated last week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 2 months ago
• chipsalliance / tilelink
  ☆31Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆86Updated last week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 8 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆100Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆169Updated 3 weeks ago
• riscv / riscv-CMOs
  ☆86Updated 3 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆48Updated last month
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated 11 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆65Updated last year
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆54Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆69Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆103Updated 2 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 8 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 2 weeks ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago