pulp-platform / culsansLinks
Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
☆37Updated last year
Alternatives and similar repositories for culsans
Users that are interested in culsans are comparing it to the libraries listed below
Sorting:
- AIA IP compliant with the RISC-V AIA spec☆42Updated 6 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆101Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- RISC-V Core Local Interrupt Controller (CLINT)☆27Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- ☆32Updated 7 months ago
- The multi-core cluster of a PULP system.☆105Updated last week
- ☆71Updated this week
- Platform Level Interrupt Controller☆41Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- ☆17Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆113Updated last week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated last year
- ☆97Updated last year
- ☆30Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆36Updated 2 years ago
- RISC-V Nox core☆66Updated 2 weeks ago
- HW Design Collateral for Caliptra RoT IP☆103Updated this week
- Simple runtime for Pulp platforms☆48Updated last week
- Generic Register Interface (contains various adapters)☆124Updated last month
- RISC-V System on Chip Template☆158Updated this week