Alternatives and similar repositories for culsans

Users that are interested in culsans are comparing it to the libraries listed below

• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last month
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆44Updated 7 months ago
• pulp-platform / clint
  RISC-V Core Local Interrupt Controller (CLINT)
  ☆28Updated 2 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated 3 weeks ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆181Updated this week
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆36Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 10 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆57Updated 2 weeks ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆67Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆43Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated 2 months ago
• pulp-platform / redmule
  ☆73Updated last week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆74Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆42Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆110Updated this week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated this week
• pulp-platform / ace
  ☆19Updated last week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 6 months ago
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆17Updated 5 months ago
• chipsalliance / tilelink
  ☆34Updated 9 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆46Updated 3 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆117Updated last week
• riscvarchive / riscv-CMOs
  ☆90Updated 2 weeks ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆40Updated last month
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆19Updated 2 months ago