pulp-platform / culsans
Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
☆30Updated 10 months ago
Alternatives and similar repositories for culsans:
Users that are interested in culsans are comparing it to the libraries listed below
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆88Updated this week
- RISC-V Core Local Interrupt Controller (CLINT)☆25Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- AIA IP compliant with the RISC-V AIA spec☆36Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated this week
- Platform Level Interrupt Controller☆37Updated 10 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- ☆88Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Simple runtime for Pulp platforms☆42Updated last week
- The multi-core cluster of a PULP system.☆85Updated last week
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆61Updated 4 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- ☆28Updated 3 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆137Updated 2 weeks ago
- RISC-V IOMMU Specification☆109Updated last week
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆28Updated last year
- ☆23Updated 3 weeks ago
- A SystemVerilog source file pickler.☆55Updated 5 months ago
- ☆42Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- Generic Register Interface (contains various adapters)☆111Updated 5 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆16Updated 3 weeks ago
- ☆11Updated 6 months ago