Verilog digital signal processing components
☆187Oct 30, 2022Updated 3 years ago
Alternatives and similar repositories for verilog-dsp
Users that are interested in verilog-dsp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog UART☆574Feb 27, 2025Updated last year
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- Verilog FT245 to AXI stream interface☆29Jun 20, 2018Updated 8 years ago
- Verilog AXI stream components for FPGA implementation☆907Feb 27, 2025Updated last year
- Verilog I2C interface for FPGA implementation☆710Feb 27, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Fully parametrizable combinatorial parallel LFSR/CRC module☆162Feb 27, 2025Updated last year
- Verilog wishbone components☆133Jan 5, 2024Updated 2 years ago
- RTL Verilog library for various DSP modules☆99Feb 17, 2022Updated 4 years ago
- Verilog PCI express components☆1,628Apr 26, 2024Updated 2 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- Verilog AXI components for FPGA implementation☆2,100Feb 27, 2025Updated last year
- A collection of demonstration digital filters☆179Jan 18, 2024Updated 2 years ago
- Verilog implementation of Mersenne Twister PRNG☆31Jun 20, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generic Register Interface (contains various adapters)☆141Updated this week
- Various HDL (Verilog) IP Cores☆926Jul 1, 2021Updated 5 years ago
- Extensible FPGA control platform☆63Apr 28, 2023Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆68Aug 21, 2025Updated 11 months ago
- Verilog Ethernet components for FPGA implementation☆3,045Feb 27, 2025Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆93Updated this week
- FIR implemention with Verilog☆50May 18, 2019Updated 7 years ago
- FPGA board-level debugging and reverse-engineering tool☆45Mar 24, 2023Updated 3 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆225Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆467Feb 13, 2026Updated 5 months ago
- AXI interface modules for Cocotb☆344Mar 13, 2026Updated 4 months ago
- Scripts for Digital Design flow control.☆17Oct 30, 2025Updated 8 months ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆235Sep 14, 2023Updated 2 years ago
- Provides a USBTMC driver for controlling instruments over USB☆23Oct 31, 2017Updated 8 years ago
- Python HPGL parsing library☆21Nov 25, 2020Updated 5 years ago
- Common SystemVerilog components☆772Updated this week
- A DDR3 memory controller in Verilog for various FPGAs☆617Oct 10, 2021Updated 4 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A simple, basic, formally verified UART controller☆344Jan 29, 2024Updated 2 years ago
- Verilog Configurable Cache☆196Jun 10, 2026Updated last month
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- synthesiseable ieee 754 floating point library in verilog☆747Mar 13, 2023Updated 3 years ago
- ☆22Jul 28, 2016Updated 10 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆228Jan 11, 2026Updated 6 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆153Oct 2, 2025Updated 9 months ago