Alternatives and similar repositories for verilog-dsp

Users that are interested in verilog-dsp are comparing it to the libraries listed below

• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 7 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆182Updated 12 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated this week
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆143Updated 11 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆93Updated last year
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆100Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆70Updated 9 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆394Updated 3 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆288Updated this week
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆156Updated 3 years ago
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 4 months ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆110Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆182Updated 3 weeks ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆144Updated 6 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆78Updated 2 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆179Updated 3 weeks ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆147Updated last week
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆133Updated 6 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆125Updated 3 years ago
• HDLForBeginners / Examples
  ☆105Updated 2 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆107Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago