alexforencich / verilog-dsp
Verilog digital signal processing components
☆126Updated 2 years ago
Alternatives and similar repositories for verilog-dsp:
Users that are interested in verilog-dsp are comparing it to the libraries listed below
- Fully parametrizable combinatorial parallel LFSR/CRC module☆143Updated 2 years ago
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆152Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆150Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- AHB3-Lite Interconnect☆84Updated 9 months ago
- DDR2 memory controller written in Verilog☆73Updated 12 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆65Updated 2 years ago
- Mathematical Functions in Verilog☆88Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Altera Advanced Synthesis Cookbook 11.0☆98Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Control and Status Register map generator for HDL projects☆109Updated this week
- A simple DDR3 memory controller☆54Updated 2 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- Control and status register code generator toolchain☆112Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆52Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Fixed Point Math Library for Verilog☆124Updated 10 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆33Updated 10 months ago
- AXI interface modules for Cocotb☆233Updated last year
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- ☆130Updated 2 years ago