Verilog digital signal processing components
☆184Oct 30, 2022Updated 3 years ago
Alternatives and similar repositories for verilog-dsp
Users that are interested in verilog-dsp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- Verilog UART☆570Feb 27, 2025Updated last year
- Verilog FT245 to AXI stream interface☆29Jun 20, 2018Updated 7 years ago
- Verilog AXI stream components for FPGA implementation☆895Feb 27, 2025Updated last year
- Verilog I2C interface for FPGA implementation☆702Feb 27, 2025Updated last year
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Feb 27, 2025Updated last year
- Verilog wishbone components☆132Jan 5, 2024Updated 2 years ago
- RTL Verilog library for various DSP modules☆98Feb 17, 2022Updated 4 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Verilog PCI express components☆1,610Apr 26, 2024Updated 2 years ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 10 years ago
- Verilog AXI components for FPGA implementation☆2,071Feb 27, 2025Updated last year
- A collection of demonstration digital filters☆175Jan 18, 2024Updated 2 years ago
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Various HDL (Verilog) IP Cores☆908Jul 1, 2021Updated 4 years ago
- Extensible FPGA control platform☆63Apr 28, 2023Updated 3 years ago
- Verilog implementation of Mersenne Twister PRNG☆31Jun 20, 2018Updated 7 years ago
- Verilog Ethernet components for FPGA implementation☆2,988Feb 27, 2025Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆68Aug 21, 2025Updated 9 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆91Feb 5, 2026Updated 4 months ago
- FPGA board-level debugging and reverse-engineering tool☆40Mar 24, 2023Updated 3 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 7 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆457Feb 13, 2026Updated 4 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AXI interface modules for Cocotb☆333Mar 13, 2026Updated 3 months ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆236Sep 14, 2023Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆332Sep 14, 2023Updated 2 years ago
- Common SystemVerilog components☆757Jun 5, 2026Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆601Oct 10, 2021Updated 4 years ago
- Python HPGL parsing library☆21Nov 25, 2020Updated 5 years ago
- A simple, basic, formally verified UART controller☆341Jan 29, 2024Updated 2 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Provides a USBTMC driver for controlling instruments over USB☆23Oct 31, 2017Updated 8 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆807Jun 12, 2026Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆149Oct 2, 2025Updated 8 months ago
- synthesiseable ieee 754 floating point library in verilog☆743Mar 13, 2023Updated 3 years ago
- ☆22Jul 28, 2016Updated 9 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- Verilog Configurable Cache☆200Jun 10, 2026Updated last week