pulp-platform / pulp-rt-examples
☆11Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for pulp-rt-examples
- ☆74Updated 10 months ago
- AHB3-Lite Interconnect☆81Updated 6 months ago
- Basic RISC-V Test SoC☆104Updated 5 years ago
- round robin arbiter☆68Updated 10 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆146Updated this week
- AMBA bus generator including AXI, AHB, and APB☆90Updated 3 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- An Open-Source Design and Verification Environment for RISC-V☆76Updated 3 years ago
- Network on Chip Implementation written in SytemVerilog☆158Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- ☆23Updated 5 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆121Updated 10 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆114Updated 4 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- SystemVerilog VIP for AMBA APB protocol☆67Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- ☆10Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆127Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago