pulp-platform / pulp-riscv-gnu-toolchainLinks
☆93Updated 3 weeks ago
Alternatives and similar repositories for pulp-riscv-gnu-toolchain
Users that are interested in pulp-riscv-gnu-toolchain are comparing it to the libraries listed below
Sorting:
- ☆118Updated 3 weeks ago
- RISC-V Verification Interface☆102Updated 3 months ago
- Basic RISC-V Test SoC☆140Updated 6 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆219Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 9 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- ☆244Updated 2 years ago
- RISC-V System on Chip Template☆159Updated 3 weeks ago
- An Open-Source Design and Verification Environment for RISC-V☆83Updated 4 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- AHB3-Lite Interconnect☆92Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆255Updated 3 months ago
- VeeR EL2 Core☆297Updated 2 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated this week
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆174Updated last week
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆224Updated last month
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆104Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆63Updated 4 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆201Updated 10 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- OpenXuantie - OpenE906 Core☆140Updated last year
- ☆187Updated last year