☆109Aug 19, 2025Updated last year
Alternatives and similar repositories for pulp-riscv-gnu-toolchain
Users that are interested in pulp-riscv-gnu-toolchain are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆128Oct 14, 2026Updated 3 weeks ago
- ☆13Jan 14, 2021Updated 5 years ago
- ☆23Mar 15, 2025Updated last year
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆503May 8, 2026Updated 5 months ago
- GNU toolchain for PULP and RISC-V☆14Mar 15, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆10Feb 27, 2020Updated 6 years ago
- Simple runtime for Pulp platforms☆56Jul 7, 2026Updated 4 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆573Nov 26, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,320Updated this week
- A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features…☆13Sep 10, 2026Updated last month
- Pulp virtual platform☆24Jul 16, 2025Updated last year
- GEMM and GEMM-Ops accelerator for PULP systems☆126Updated this week
- UNSUPPORTED INTERNAL toolchain builds☆50Sep 13, 2026Updated last month
- An open-source microcontroller system based on RISC-V☆1,074Feb 6, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆289Nov 6, 2024Updated 2 years ago
- The multi-core cluster of a PULP system.☆123Oct 27, 2026Updated last week
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆45Oct 29, 2023Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆232Jan 11, 2026Updated 9 months ago
- ☆36Mar 8, 2023Updated 3 years ago
- Neural Engine, 16 input channels☆20Oct 31, 2022Updated 4 years ago
- CORE-V Family of RISC-V Cores☆380Mar 31, 2026Updated 7 months ago
- FreeRTOS for PULP☆16Jul 24, 2023Updated 3 years ago
- ☆28Apr 17, 2026Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Functional verification project for the CORE-V family of RISC-V cores.☆739Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Jul 16, 2026Updated 3 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆255Oct 26, 2026Updated last week
- Common SystemVerilog components☆814Sep 18, 2026Updated last month
- pulp_soc is the core building component of PULP based SoCs☆87Jul 17, 2026Updated 3 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆295Oct 28, 2026Updated last week
- ☆10Aug 3, 2026Updated 3 months ago
- ☆100Oct 18, 2023Updated 3 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆333Sep 15, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆180Updated this week
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- ☆15Oct 2, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆140Jul 11, 2025Updated last year
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,162Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated 2 years ago
- ☆143Feb 29, 2024Updated 2 years ago