Alternatives and similar repositories for pulp-sdk

Users that are interested in pulp-sdk are comparing it to the libraries listed below

• pulp-platform / pulp-riscv-gnu-toolchain
  ☆89Updated this week
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆98Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆139Updated 6 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆173Updated 8 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆184Updated 3 weeks ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆122Updated 4 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆240Updated 2 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆174Updated 6 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated 2 weeks ago
• chipsalliance / VeeR-ISS
  ☆141Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆138Updated 2 weeks ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆186Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆73Updated last month
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆131Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 7 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆252Updated 2 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆205Updated this week
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆90Updated 7 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago