pulp-platform / pulp-sdk
☆109Updated last week
Alternatives and similar repositories for pulp-sdk:
Users that are interested in pulp-sdk are comparing it to the libraries listed below
- ☆86Updated last month
- Basic RISC-V Test SoC☆122Updated 6 years ago
- Fabric generator and CAD tools☆178Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆90Updated last week
- VeeR EL2 Core☆274Updated last week
- A demo system for Ibex including debug support and some peripherals☆63Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆250Updated 2 weeks ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆92Updated last year
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆126Updated 5 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆178Updated this week
- RISC-V Verification Interface☆89Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆200Updated last week
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- ☆232Updated 2 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- An Open-Source Design and Verification Environment for RISC-V☆80Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆235Updated 6 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- OpenXuantie - OpenE902 Core☆143Updated 10 months ago
- AMBA bus generator including AXI, AHB, and APB☆100Updated 3 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆212Updated 4 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆210Updated 3 weeks ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆136Updated 7 months ago
- SystemVerilog modules and classes commonly used for verification☆47Updated 4 months ago