pulp-platform / pulp-sdkLinks
☆111Updated last month
Alternatives and similar repositories for pulp-sdk
Users that are interested in pulp-sdk are comparing it to the libraries listed below
Sorting:
- ☆87Updated 4 months ago
- Basic RISC-V Test SoC☆137Updated 6 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆95Updated 3 weeks ago
- RISC-V Verification Interface☆97Updated last month
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆181Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆183Updated 2 years ago
- SystemC/TLM-2.0 Co-simulation framework☆251Updated last month
- RISC-V System on Chip Template☆158Updated 3 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆168Updated 7 months ago
- ☆139Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- VeeR EL2 Core☆288Updated 2 weeks ago
- ☆239Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆260Updated 2 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆271Updated this week
- RISC-V Integration for PYNQ☆175Updated 6 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆129Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆111Updated this week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 9 months ago
- The multi-core cluster of a PULP system.☆105Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆271Updated 4 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆202Updated 8 months ago
- Arduino compatible Risc-V Based SOC☆153Updated last year
- Vector processor for RISC-V vector ISA☆121Updated 4 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆431Updated 2 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- CORE-V Family of RISC-V Cores☆278Updated 5 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆73Updated last month