pulp-platform / pulp-sdkLinks
☆121Updated last month
Alternatives and similar repositories for pulp-sdk
Users that are interested in pulp-sdk are comparing it to the libraries listed below
Sorting:
- ☆97Updated 4 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆98Updated 5 months ago
- Basic RISC-V Test SoC☆162Updated 6 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated last week
- RISC-V Integration for PYNQ☆179Updated 6 years ago
- RISC-V Verification Interface☆132Updated last week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆144Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆183Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last week
- ☆250Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- RISC-V System on Chip Template☆159Updated 4 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- IEEE 754 floating point unit in Verilog☆150Updated 9 years ago
- Network on Chip Implementation written in SytemVerilog☆195Updated 3 years ago
- Learn systemC with examples☆125Updated 3 years ago
- SystemC/TLM-2.0 Co-simulation framework☆263Updated 7 months ago
- A demo system for Ibex including debug support and some peripherals☆85Updated last month
- RISC-V Virtual Prototype☆182Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- ☆150Updated 2 years ago
- Vector processor for RISC-V vector ISA☆131Updated 5 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated 11 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆232Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆287Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆251Updated this week
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Fixed Point Math Library for Verilog☆145Updated 11 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year