☆124Mar 13, 2026Updated last week
Alternatives and similar repositories for pulp-sdk
Users that are interested in pulp-sdk are comparing it to the libraries listed below
Sorting:
- ☆103Aug 19, 2025Updated 7 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆463May 15, 2025Updated 10 months ago
- Simple runtime for Pulp platforms☆52Feb 2, 2026Updated last month
- FreeRTOS for PULP☆16Jul 24, 2023Updated 2 years ago
- ☆13Jan 14, 2021Updated 5 years ago
- Tool to connect the workstation to the pulp targets abd interact with them☆11Oct 22, 2020Updated 5 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆541Nov 26, 2024Updated last year
- NEural Minimizer for pytOrch☆47Jul 25, 2024Updated last year
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆93Aug 4, 2025Updated 7 months ago
- Pulp virtual platform☆24Jul 16, 2025Updated 8 months ago
- ☆10Feb 27, 2020Updated 6 years ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- ☆92Oct 18, 2023Updated 2 years ago
- ☆23Mar 15, 2025Updated last year
- ☆35Mar 8, 2023Updated 3 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆663Mar 8, 2026Updated last week
- Neural Engine, 16 input channels☆16Oct 31, 2022Updated 3 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆30Jan 29, 2026Updated last month
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 2 months ago
- SDK for Greenwaves Technologies' GAP8 IoT Application Processor☆151May 31, 2024Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 2 months ago
- ☆38Updated this week
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated last week
- ☆11Jun 28, 2020Updated 5 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆229Nov 22, 2023Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- An open-source microcontroller system based on RISC-V☆1,012Feb 6, 2024Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆338Dec 11, 2024Updated last year
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆122Mar 6, 2026Updated 2 weeks ago
- ☆23Oct 8, 2019Updated 6 years ago
- ☆24May 26, 2022Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,797Feb 17, 2026Updated last month
- Common SystemVerilog components☆728Updated this week
- A library to train and deploy quantised Deep Neural Networks☆27Dec 18, 2024Updated last year
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆22Nov 21, 2020Updated 5 years ago
- VeeR EL2 Core☆323Mar 12, 2026Updated last week
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Sep 9, 2025Updated 6 months ago
- Labs for the Ibex Demo System☆17Nov 18, 2023Updated 2 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆156Oct 31, 2024Updated last year