pulp-platform / hwpe-streamLinks
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
☆20Updated 2 weeks ago
Alternatives and similar repositories for hwpe-stream
Users that are interested in hwpe-stream are comparing it to the libraries listed below
Sorting:
- An example Hardware Processing Engine☆11Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆27Updated 6 years ago
- ☆37Updated 6 years ago
- SoC Based on ARM Cortex-M3☆33Updated 5 months ago
- ☆30Updated last month
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆12Updated last month
- HLS for Networks-on-Chip☆36Updated 4 years ago
- ☆19Updated 2 weeks ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆30Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- The memory model was leveraged from micron.☆24Updated 7 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- DUTH RISC-V Microprocessor☆22Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆20Updated 2 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- SRAM☆22Updated 5 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago