pulp-platform / hwpe-stream
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
☆19Updated last month
Alternatives and similar repositories for hwpe-stream
Users that are interested in hwpe-stream are comparing it to the libraries listed below
Sorting:
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 11 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 6 months ago
- ☆33Updated 6 years ago
- ☆27Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆16Updated 4 years ago
- CNN accelerator☆27Updated 7 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- SRAM☆22Updated 4 years ago
- ☆27Updated last month
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Ratatoskr NoC Simulator☆25Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated last year
- General Purpose AXI Direct Memory Access☆49Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆21Updated last year
- SoC Based on ARM Cortex-M3☆30Updated last week
- ☆27Updated 4 years ago
- ☆48Updated 6 years ago
- ☆25Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆18Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- verification of simple axi-based cache☆18Updated 6 years ago