An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
☆17Feb 29, 2024Updated 2 years ago
Alternatives and similar repositories for SCAIE-V
Users that are interested in SCAIE-V are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Scalable Interface for RISC-V ISA Extensions☆26Apr 7, 2026Updated last month
- Mirror of the now discontinued ORCA RISC-V processor from VectorBlox.☆11Feb 11, 2020Updated 6 years ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 9 months ago
- ☆33Jan 7, 2025Updated last year
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆22Mar 20, 2025Updated last year
- An open-source implementation of the VADL processor description language.☆49Updated this week
- A Risc-V SoC for Tiny Tapeout☆53Dec 2, 2025Updated 5 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆56Feb 6, 2020Updated 6 years ago
- Collection of kernel accelerators optimised for LLM execution☆32Feb 26, 2026Updated 3 months ago
- DNN Compiler for Heterogeneous SoCs☆68May 8, 2026Updated 3 weeks ago
- ☆25Jun 3, 2024Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆10Feb 27, 2023Updated 3 years ago
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Mar 29, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- wafer.space GF180MCU Run 1☆30Apr 27, 2026Updated last month
- ☆21May 8, 2025Updated last year
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆223May 13, 2026Updated 2 weeks ago
- Xtext project to parse CoreDSL files☆23Apr 29, 2026Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆482May 8, 2026Updated 3 weeks ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆64Nov 14, 2025Updated 6 months ago
- Module for LST retrieval from Landsat-8/TIRS imagery based on practical split-window algorithm + covariance-variance ratio (SWCVR) method☆11May 27, 2025Updated last year
- SoC for CQU Dual Issue Machine☆12Sep 20, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- MIPS 57条指令五级流水线cpu (verilog实现+详细注释)☆11Jan 11, 2022Updated 4 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- ☆48Jun 27, 2024Updated last year
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆19Dec 4, 2020Updated 5 years ago
- SiliconCompiler Design Gallery☆64May 18, 2026Updated last week
- Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.☆46Sep 1, 2025Updated 8 months ago
- ☆45Jun 30, 2024Updated last year
- Project Peppercorn GateMate Test Cases☆16Feb 25, 2026Updated 3 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆53Mar 31, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A library of VHDL components for Neural Networks☆21Sep 23, 2021Updated 4 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- RISC-V Virtual Prototype☆47Oct 1, 2021Updated 4 years ago
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆13Jul 16, 2024Updated last year
- microKanren sagittarius/larceny☆11Jun 13, 2015Updated 10 years ago
- Custom 6502 Video Game Console☆14May 8, 2026Updated 3 weeks ago
- Provide user-defined initialization semantics for arithmetic types.☆11Mar 29, 2026Updated 2 months ago