esa-tu-darmstadt / SCAIE-VLinks
An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
☆16Updated last year
Alternatives and similar repositories for SCAIE-V
Users that are interested in SCAIE-V are comparing it to the libraries listed below
Sorting:
- ☆34Updated 5 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated last month
- ☆15Updated 3 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 3 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆41Updated 8 months ago
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 11 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆73Updated last week
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Advanced Architecture Labs with CVA6☆67Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- ☆48Updated 4 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- ☆46Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- Public release☆57Updated 6 years ago
- ☆32Updated 3 months ago
- RISC-V Matrix Specification☆22Updated 9 months ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- ☆31Updated 10 months ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆41Updated last month
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆36Updated 3 months ago
- ☆18Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆53Updated 6 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆23Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year