esa-tu-darmstadt / SCAIE-VLinks
An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
☆16Updated last year
Alternatives and similar repositories for SCAIE-V
Users that are interested in SCAIE-V are comparing it to the libraries listed below
Sorting:
- ☆16Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆80Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆43Updated last week
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated 3 weeks ago
- ☆18Updated 2 weeks ago
- ☆56Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆43Updated 9 months ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆41Updated 4 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆61Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- ☆35Updated this week
- FSA: Fusing FlashAttention within a Single Systolic Array☆53Updated 2 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆109Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- CGRA framework with vectorization support.☆35Updated this week
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- ☆47Updated 9 months ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆53Updated 6 months ago