pulp-platform / pulp-builderLinks
☆10Updated 5 years ago
Alternatives and similar repositories for pulp-builder
Users that are interested in pulp-builder are comparing it to the libraries listed below
Sorting:
- ☆23Updated 8 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated this week
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆29Updated 9 months ago
- SoC Based on ARM Cortex-M3☆34Updated 6 months ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Updated 2 weeks ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- Simple single-port AXI memory interface☆47Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- Design and UVM-TB of RISC -V Microprocessor☆29Updated last year
- SystemVerilog modules and classes commonly used for verification☆51Updated last week
- ☆22Updated 6 years ago
- ☆21Updated 5 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆13Updated 3 weeks ago
- Connecting SystemC with SystemVerilog☆41Updated 13 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- fpga verilog risc-v rv32i cpu☆13Updated 2 years ago
- ☆31Updated 5 years ago
- Contains commonly used UVM components (agents, environments and tests).☆31Updated 7 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 weeks ago
- ☆32Updated last week
- [UNRELEASED] FP div/sqrt unit for transprecision☆24Updated 2 months ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago