pulp-platform / pulp-builderLinks
☆10Updated 5 years ago
Alternatives and similar repositories for pulp-builder
Users that are interested in pulp-builder are comparing it to the libraries listed below
Sorting:
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆18Updated last week
- ☆23Updated 7 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- ☆30Updated 5 years ago
- SoC Based on ARM Cortex-M3☆33Updated 5 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 2 weeks ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated 5 months ago
- ☆30Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- ☆21Updated 6 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆64Updated 4 years ago
- Simple single-port AXI memory interface☆46Updated last year
- SystemVerilog modules and classes commonly used for verification☆50Updated 9 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 months ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆64Updated 3 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Network on Chip for MPSoC☆28Updated 5 months ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆35Updated 10 years ago