pulp-platform / hci
Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
☆12Updated this week
Alternatives and similar repositories for hci:
Users that are interested in hci are comparing it to the libraries listed below
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 2 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆31Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆29Updated 8 months ago
- Synthesisable SIMT-style RISC-V GPGPU☆30Updated this week
- The multi-core cluster of a PULP system.☆65Updated this week
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆23Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 months ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 10 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Updated 4 years ago
- Intel Compiler for SystemC☆24Updated last year
- ☆52Updated 2 years ago
- Verilog behavioral description of various memories☆30Updated 2 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 10 months ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆13Updated last week
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆42Updated 2 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Updated last year
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆29Updated last month