pulp-platform / hci

Related projects: ⓘ

• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆19Updated 3 weeks ago
• ucb-bar / nvdla-wrapper
  Wraps the NVDLA project for Chipyard integration
  ☆20Updated 6 months ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆26Updated 4 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆26Updated 4 months ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆36Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 7 months ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆23Updated 4 years ago
• FPGA-Research-Manchester / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆13Updated 4 years ago
• chipsalliance / fpga-interchange-schema
  ☆51Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆55Updated this week
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆17Updated 2 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆18Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆26Updated last month
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆28Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆66Updated 4 months ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• IObundle / iob-mem
  Verilog behavioral description of various memories
  ☆30Updated 2 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆29Updated 3 years ago
• PrincetonUniversity / Duet
  ☆15Updated last year
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆11Updated 6 months ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆27Updated last week
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆16Updated 2 weeks ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆34Updated 2 years ago
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆21Updated 2 years ago
• pulp-platform / redmule
  ☆31Updated last month
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆19Updated 2 years ago
• pulp-platform / axi_llc
  ☆17Updated last week
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆28Updated 6 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆21Updated 2 years ago