fpgasystems / erbiumLinks
Business Rule Engine Hardware Accelerator
☆13Updated 4 years ago
Alternatives and similar repositories for erbium
Users that are interested in erbium are comparing it to the libraries listed below
Sorting:
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 8 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 9 months ago
- ☆22Updated 8 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 4 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆31Updated last week
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- Advanced Debug Interface☆15Updated 4 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Network on Chip for MPSoC☆26Updated last week
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- CNN accelerator☆27Updated 7 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- SystemVerilog Logger☆17Updated 2 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆20Updated 11 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago