pulp-platform / chimera
☆16Updated this week
Alternatives and similar repositories for chimera:
Users that are interested in chimera are comparing it to the libraries listed below
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- ☆57Updated this week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- Wraps the NVDLA project for Chipyard integration☆20Updated 2 weeks ago
- Simple runtime for Pulp platforms☆45Updated last month
- Wrapper for ETH Ariane Core☆19Updated last month
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- This repo includes XiangShan's function units☆20Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆34Updated this week
- ☆11Updated 4 years ago
- ☆25Updated this week
- The multi-core cluster of a PULP system.☆89Updated 3 weeks ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆14Updated 5 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A high-efficiency system-on-chip for floating-point compute workloads.☆30Updated 3 months ago
- Recent updates and features added to the RVfpga course developed by Imagination Technologies.☆14Updated this week
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 3 weeks ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- ☆32Updated 5 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- ☆9Updated last year
- ☆18Updated this week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated last week
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆30Updated last year