pulp-platform / chimeraLinks
☆16Updated 3 weeks ago
Alternatives and similar repositories for chimera
Users that are interested in chimera are comparing it to the libraries listed below
Sorting:
- ☆62Updated this week
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 2 weeks ago
- Simple runtime for Pulp platforms☆48Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 2 months ago
- Wraps the NVDLA project for Chipyard integration☆21Updated last month
- Reconfigurable Binary Engine☆16Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- A high-efficiency system-on-chip for floating-point compute workloads.☆35Updated 4 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 7 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆15Updated 6 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆33Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆25Updated this week
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Recent updates and features added to the RVfpga course developed by Imagination Technologies.☆16Updated last week
- The multi-core cluster of a PULP system.☆97Updated this week
- The PE for the second generation CGRA (garnet).☆17Updated last month
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- ☆11Updated 4 years ago
- Pulp virtual platform☆23Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- ⛔ DEPRECATED ⛔ HERO Software Development Kit☆20Updated 3 years ago
- ☆35Updated 10 months ago