pulp-platform / bigpulp
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
☆50Updated 3 years ago
Alternatives and similar repositories for bigpulp:
Users that are interested in bigpulp are comparing it to the libraries listed below
- FPGA reference design for the the Swerv EH1 Core☆70Updated 5 years ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- The multi-core cluster of a PULP system.☆69Updated this week
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- ☆44Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- ☆42Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated this week
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆85Updated 5 years ago
- ☆41Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 4 months ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- Chisel Cheatsheet☆32Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆35Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- ☆77Updated 2 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆99Updated 3 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 5 years ago