pulp-platform / bigpulp
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
☆51Updated 3 years ago
Alternatives and similar repositories for bigpulp:
Users that are interested in bigpulp are comparing it to the libraries listed below
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Verilator open-source SystemVerilog simulator and lint system☆35Updated this week
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆86Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆47Updated last month
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆64Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 10 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆67Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated this week
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆45Updated 4 years ago