pulp-platform / pulp-nnLinks
☆85Updated 2 years ago
Alternatives and similar repositories for pulp-nn
Users that are interested in pulp-nn are comparing it to the libraries listed below
Sorting:
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆87Updated 3 weeks ago
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆88Updated 2 months ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆87Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆60Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 8 months ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆164Updated 3 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- ☆46Updated 5 years ago
- ☆65Updated 3 years ago
- ☆35Updated 6 years ago
- ☆80Updated last week
- Train and deploy LUT-based neural networks on FPGAs☆99Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆144Updated 5 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- ☆71Updated 5 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆95Updated this week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- ☆34Updated 2 years ago
- ☆70Updated 6 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- ☆35Updated this week
- ☆40Updated 5 years ago