Alternatives and similar repositories for TeraNoC

Users that are interested in TeraNoC are comparing it to the libraries listed below

• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆62Updated last month
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆45Updated 2 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆70Updated 3 years ago
• antmicro / nvme-verilog-pcie
  ☆80Updated 3 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆82Updated 11 years ago
• oprecomp / DDR4_controller
  ☆74Updated 5 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 6 months ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆72Updated 8 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆23Updated 10 months ago
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆20Updated 10 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆57Updated last month
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆115Updated 3 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆20Updated 7 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆26Updated 9 years ago
• ucb-bar / ucie
  An open-source UCIe implementation
  ☆82Updated last week
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆48Updated this week
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago